UPD78044F datasheet(62/472 Pages) NEC

62 / 472 page

Chapter 3

CPU Architecture

User’s Manual U16504EE1V1UD00

3.2 Processor Registers

The µPD780828A Subseries units incorporate the following processor registers.

3.2.1 Control registers

The control registers control the program sequence, statuses, and stack memory. The control registers

consist of a program counter, a program status word and a stack pointer.

(1)

Program counter (PC)

The program counter is a 16-bit register which holds the address information of the next program

to be executed.

In normal operation, the PC is automatically incremented according to the number of bytes of the

instruction to be fetched. When a branch instruction is executed, immediate data and register con-

tents are set.

RESET input sets the reset vector table values at addresses 0000H and 0001H to the program

counter.

Figure 3-9:

Program Counter Configuration

(2)

Program status word (PSW)

The program status word is an 8-bit register consisting of various flags to be set/reset by instruc-

tion execution.

Program status word contents are automatically stacked upon interrupt request generation or

PUSH PSW instruction execution and are automatically reset upon execution of the RETB, RETI

and POP PSW instructions.

RESET input sets the PSW to 02H.

Figure 3-10:

Program Status Word Configuration

RBS1

RBS0

ISP

UPD78044F Datasheet(PDF) 62 Page - NEC