UPD78044F datasheet(18/472 Pages) NEC

18 / 472 page

User’s Manual U16504EE1V1UD00

Figure 16-29:

Receive Identifier ...................................................................................................... 274

Figure 16-30:

Receive Data ............................................................................................................ 275

Figure 16-31:

Identifier Compare with Mask .................................................................................... 277

Figure 16-32:

Control Bits for Mask Identifier ................................................................................. 278

Figure 16-33:

Mask Identifier .......................................................................................................... 279

Figure 16-34:

CAN Control Register (1/2) ....................................................................................... 280

Figure 16-35:

DCAN Support........................................................................................................... 281

Figure 16-36:

Time Stamp Function ................................................................................................283

Figure 16-37:

SOFOUT Toggle Function......................................................................................... 283

Figure 16-38:

Global Time System Function ................................................................................... 283

Figure 16-39:

CAN Error Status Register (1/3) ............................................................................... 284

Figure 16-40:

Transmit Error Counter ............................................................................................. 287

Figure 16-41:

Receive Error Counter .............................................................................................. 287

Figure 16-42:

Message Count Register (MCNT) (1/2) .................................................................... 288

Figure 16-43:

Bit Rate Prescaler (1/2) ............................................................................................ 290

Figure 16-44:

Synchronization Control Registers 0 and 1 (1/2) ..................................................... 292

Figure 16-45:

Transmit Control Register (1/2) ................................................................................ 296

Figure 16-46:

Receive Message Register ....................................................................................... 298

Figure 16-47:

Mask Control Register (1/2) ...................................................................................... 299

Figure 16-48:

Redefinition Control Register (1/2) ........................................................................... 302

Figure 16-49:

Initialization Flow Chart ............................................................................................. 309

Figure 16-50:

Transmit Preparation ................................................................................................. 310

Figure 16-51:

Transmit Abort ........................................................................................................... 311

Figure 16-52:

Handling of Semaphore Bits by DCAN-Module......................................................... 312

Figure 16-53:

Receive with Interrupt, Software Flow ....................................................................... 313

Figure 16-54:

Receive, Software Polling..........................................................................................314

Figure 17-1:

LCD Controller/Driver Block Diagram........................................................................ 316

Figure 17-2:

LCD Clock Select Circuit Block Diagram................................................................... 316

Figure 17-3:

LCD Display Mode Register (LCDM) Format ............................................................ 317

Figure 17-4:

LCD Display Control Register (LCDC) Format .......................................................... 318

Figure 17-5:

Relationship between LCD Display Data Memory Contents

and Segment/Common Outputs319

Figure 17-6:

Common Signal Waveform........................................................................................ 321

Figure 17-7:

Common Signal and Segment Signal Voltages and Phases..................................... 321

Figure 17-8:

Example of Connection of LCD Drive Power Supply (1/2) ........................................ 322

Figure 17-9:

4-Time-Division LCD Display Pattern and Electrode Connections............................ 324

Figure 17-10:

4-Time-Division LCD Panel Connection Example ..................................................... 325

Figure 17-11:

4-Time-Division LCD Drive Waveform Examples (1/3 Bias Method) ........................ 326

Figure 17-12:

LCD Timer Control Register (LCDTM) Format .......................................................... 327

Figure 18-1:

Sound Generator Block Diagram............................................................................... 329

Figure 18-2:

Concept of Each Signal ............................................................................................. 330

Figure 18-3:

Sound Generator Control Register (SGCR) Format (1/2) ......................................... 331

Figure 18-4:

Sound Generator Buzzer Control Register (SGBR) Format...................................... 333

Figure 18-5:

Sound Generator Amplitude Register (SGAM) Format ............................................. 334

Figure 18-6:

Sound Generator Output Operation Timing............................................................... 335

Figure 18-7:

Sound Generator Output Operation Timing............................................................... 336

Figure 19-1:

Meter Controller/Driver Block Diagram...................................................................... 337

Figure 19-2:

1-bit Addition Circuit Block Diagram .......................................................................... 338

Figure 19-3:

Timer Mode Control Register (MCNTC) Format........................................................ 341

Figure 19-4:

Compare Control Register n (MCMPCn) Format ...................................................... 342

Figure 19-5:

Port Mode Control Register (PMC) Format (1/2)....................................................... 343

Figure 19-6:

Meter Controller/Driver Clock Register (SMSWI) Format.......................................... 345

Figure 19-7:

Restart Timing after Count Stop (Count Start Æ Count Stop Æ Count Start) ........... 346

Figure 19-8:

Update of PWM data ................................................................................................. 347

Figure 19-9:

Timing in 1-bit Addition Circuit Operation .................................................................. 348

Figure 19-10:

Timing of Output with 1 Clock Shifted ....................................................................... 349

Figure 20-1:

Basic Configuration of Interrupt Function (1/2).......................................................... 353

Figure 20-2:

Interrupt Request Flag Register Format .................................................................... 356

UPD78044F Datasheet(PDF) 18 Page - NEC

UPD78044F Datasheet(HTML) 18 Page - NEC

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL