UPD78044F datasheet(77/472 Pages) NEC

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Chapter 3

CPU Architecture

User’s Manual U16504EE1V1UD00

3.4.4 Short direct addressing

The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction

word.

The fixed space to which this addressing is applied to is the 256-byte space, from FE20H to FF1FH. An

internal high-speed RAM and a special function register (SFR) are mapped at FE20H to FEFFH and

FF00H to FF1FH, respectively.

The SFR area where short direct addressing is applied (FF00H to FF1FH) is a part of the SFR area. In

this area, ports which are frequently accessed in a program, a compare register of the timer/event

counter, and a capture register of the timer/event counter are mapped and these SFRs can be manipu-

lated with a small number of bytes and clocks.

When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H

to 1FH, bit 8 is set to 1. Refer to Figure 3-21 below.

Operand format

Figure 3-21:

Short direct addressing

(a) Description example

MOV 0FE30H, #50H; when setting saddr to FE30H and immediate data to 50H.

(b) Illustration

Table 3-9:

Short direct addressing

Identifier

Description

saddr

Label of FE20H to FF1FH immediate data

saddrp

Label of FE20H to FF1FH immediate data (even address only)

Operation code

00010001

OP code

00110000

30H (saddr-offset)

01010000

50H (immediate data)

When 8-bit immediate data is 20H to FFH,

= 0

When 8-bit immediate data is 00H to 1FH,

= 1

Short Direct Memory

Effective Address

111111

OP code

saddr-offset

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