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UPD78044F Datasheet(PDF) 81 Page - NEC |
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UPD78044F Datasheet(HTML) 81 Page - NEC |
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81 / 472 page  81 Chapter 3 CPU Architecture User’s Manual U16504EE1V1UD00 3.4.8 Based indexed addressing The B or C register contents specified in an instruction are added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. The HL, B, and C registers to be accessed are registers in the register bank specified with the register bank select flag (RBS0 and RBS1). Addition is performed by expanding the contents of the B or C register as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces. Operand format Figure 3-25: Based indexed addressing description example In the case of MOV A, [HL + B] Table 3-13: Based indexed addressing Identifier Description [HL + B], [HL + C] Operation code 10101011 |
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