UPD78044F datasheet(63/472 Pages) NEC

63 / 472 page

Chapter 3

CPU Architecture

User’s Manual U16504EE1V1UD00

(a) Interrupt enable flag (IE)

This flag controls the interrupt request acknowledge operations of the CPU.

When 0, the IE is set to interrupt disabled (DI) status. All interrupts except non-maskable interrupt

are disabled.

When 1, the IE is set to interrupt enabled (EI) status and interrupt request acknowledge is control-

led with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources, and a

priority specification flag.

The IE is reset to (0) upon DI instruction execution or interrupt request acknowledgement and is

set to (1) upon EI instruction execution.

(b) Zero flag (Z)

When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.

These are 2-bit flags to select one of the four register banks.

In these flags, the 2-bit information which indicates the register bank selected by SEL RBn instruc-

tion execution is stored.

(d) Auxiliary carry flag (AC)

If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in

all other cases.

(e) In-service priority flag (ISP)

This flag manages the priority of acknowledge able maskable vectored interrupts. When 0,

acknowledgment of the vectored interrupt request specified to low-order priority with the priority

specify flag registers (PR0L, PR0H, and PR1L) is disabled. Whether an actual interrupt request is

acknowledged or not is controlled with the interrupt enable flag (IE).

(f) Carry flag (CY)

This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-

out value upon rotate instruction execution and functions as a bit accumulator during bit manipula-

tion instruction execution.

UPD78044F Datasheet(PDF) 63 Page - NEC