UPD78044F datasheet(16/472 Pages) NEC

16 / 472 page

User’s Manual U16504EE1V1UD00

Figure 6-6:

Timing of Pulse Width Measurement Operation by Using the Free Running

Counter and One Capture Register (with Both Edges Specified).............................. 120

Figure 6-7:

CR2m Capture Operation with Rising Edge Specified .............................................. 121

Figure 6-8:

Timing of Pulse Width Measurement Operation by Free Running Counter

(with Both Edges Specified) ...................................................................................... 122

Figure 6-9:

16-Bit Timer Register Start Timing ............................................................................ 123

Figure 6-10:

Capture Register Data Retention Timing................................................................... 123

Figure 7-1:

8-Bit Timer/Event Counter 50 Block Diagram............................................................ 129

Figure 7-2:

8-Bit Timer/Event Counter 51 Block Diagram............................................................ 130

Figure 7-3:

Block Diagram of 8-Bit Timer/Event Counters 50 and 51 Output Control Circuit ...... 130

Figure 7-4:

Timer Clock Select Register 50 Format..................................................................... 132

Figure 7-5:

Timer Clock Select Register 51 Format..................................................................... 133

Figure 7-6:

8-Bit Timer Mode Control Register 50 Format........................................................... 134

Figure 7-7:

8-Bit Timer Mode Control Register 51 Format (1/2) .................................................. 135

Figure 7-8:

Port Mode Register 3 Format .................................................................................... 136

Figure 7-9:

Port Mode Register 9 Format .................................................................................... 137

Figure 7-10:

8-Bit Timer Mode Control Register Settings for Interval Timer Operation ................. 138

Figure 7-11:

Interval Timer Operation Timings (1/3)...................................................................... 139

Figure 7-12:

8-Bit Timer Mode Control Register Setting for External Event Counter Operation.... 143

Figure 7-13:

External Event Counter Operation Timings (with Rising Edge Specified) ................. 143

Figure 7-14:

8-Bit Timer Mode Control Register Settings for Square-Wave Output Operation ..... 144

Figure 7-15:

Square-wave Output Operation Timing ..................................................................... 145

Figure 7-16:

8-Bit Timer Control Register Settings for PWM Output Operation ............................ 146

Figure 7-17:

PWM Output Operation Timing (Active high setting)................................................. 147

Figure 7-18:

PWM Output Operation Timings (CRn0 = 00H, active high setting) ......................... 147

Figure 7-19:

PWM Output Operation Timings (CRn = FFH, active high setting) ........................... 148

Figure 7-20:

PWM Output Operation Timings (CRn changing, active high setting)....................... 148

Figure 7-21:

8-Bit Timer Mode Control Register Settings for 16-Bit Interval Timer Operation....... 149

Figure 7-22:

16-Bit Resolution Cascade Mode (with TM50 and TM51)......................................... 151

Figure 7-23:

8-bit Timer Registers 50 and 51 Start Timings .......................................................... 153

Figure 7-24:

External Event Counter Operation Timings ............................................................... 153

Figure 7-25:

Timings after Compare Register Change during Timer Count Operation ................. 154

Figure 8-1:

8-Bit Timer/Event Counter 52 Block Diagram............................................................ 156

Figure 8-2:

Timer Clock Select Register 52 Format..................................................................... 157

Figure 8-3:

8-Bit Timer Output Control Register Format.............................................................. 158

Figure 8-4:

8-Bit Timer Mode Control Register Settings for Interval Timer Operation ................. 159

Figure 8-5:

Interval Timer Operation Timings (1/3)...................................................................... 159

Figure 9-1:

Block Diagram of Watch Timer.................................................................................. 163

Figure 9-2:

Watch Timer Mode Control Register (WTM) Format (1/2) ........................................ 165

Figure 9-3:

Operation Timing of Watch Timer/Interval Timer....................................................... 168

Figure 10-1:

Watchdog Timer Block Diagram................................................................................ 171

Figure 10-2:

Timer Clock Select Register 2 Format....................................................................... 172

Figure 10-3:

Watchdog Timer Mode Register Format ................................................................... 173

Figure 11-1:

Remote Controlled Output Application Example ....................................................... 177

Figure 11-2:

Clock Output Control Circuit Block Diagram.............................................................. 178

Figure 11-3:

Timer Clock Select Register 0 Format....................................................................... 179

Figure 11-4:

Port Mode Register 6 Format .................................................................................... 180

Figure 12-1:

A/D Converter Block Diagram ................................................................................... 181

Figure 12-2:

Power-Fail Detection Function Block Diagram .......................................................... 182

Figure 12-3:

A/D Converter Mode Register (ADM1) Format.......................................................... 184

Figure 12-4:

Analog Input Channel Specification Register (ADS1) Format ................................... 185

Figure 12-5:

Power-Fail Compare Mode Register (PFM) Format.................................................. 186

Figure 12-6:

Power-fail compare threshold value register (PFT) ................................................... 186

Figure 12-7:

Basic Operation of 8-Bit A/D Converter..................................................................... 187

Figure 12-8:

Relation between Analog Input Voltage and A/D Conversion Result ........................ 189

Figure 12-9:

A/D Conversion ......................................................................................................... 191

Figure 12-10:

Example Method of Reducing Current Consumption in Standby Mode .................... 192

Figure 12-11:

Analog Input Pin Handling ......................................................................................... 193

UPD78044F Datasheet(PDF) 16 Page - NEC

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