ECE1200 datasheet(21/87 Pages) MICROCHIP

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 2018-2021 Microchip Technology Inc.

DS00003093C Draft-page 21

ECE1200

4.4

Power, Clocks and Reset

This section defines the Power, Clock, and Reset parameters of the block.

4.4.1

POWER DOMAINS

4.4.2

CLOCKING

The LPC Interface runs from a 48MHz internal reference, 48 MHz Ring Oscillator, which is derived from the SUSCLK

input. In turn, it generates the 24MHz timebase for the LPC clocks.

4.4.3

RESETS

For the sequences of Power and Reset state transitions, see Section 9.7, "System Power State Transition Diagrams,"

on page 70.

4.5

LPC Controller Description

The LPC Controller is compliant with the Intel® Low Pin Count (LPC) Interface Specification, v1.1. Section 4.5.1, "Cycle

Types Generated" further clarifies which LPC Interface features have been implemented and qualifies any system spe-

cific requirements.

The LPC Controller accepts all eSPI I/O and Memory traffic that is directed to it from the Chipset, and passes it to the

LPC bus except for the two I/O addresses used for accessing its internal register set (see Section 6.0, "Device Register

Set and Initialization," on page 33). Traffic that is unclaimed or rejected on the LPC bus may optionally be detected and

reported to the Chipset by selectable eSPI mechanisms.

Slave devices on LPC may use the SER_IRQ mechanism to notify the host of an event.See Section 4.7, "Serial IRQ,"

on page 23.

The CLKRUN# feature is provided, allowing negotiation with LPC slave devices to turn off the LPC clock(s) as desired.

4.5.1

CYCLE TYPES GENERATED

The following cycle types are generated by the LPC Interface Controller. Note that they are all 1 byte in length. eSPI I/O

or Memory cycles that are larger than 1 byte are allowed, and are broken down into individual bytes, transferred least-

significant byte first.

Name

Description

LPC_EN

from PCH_PWROK

(VCC / Main / S0 On)

The LPC Interface block is powered by VTR_33 and VTR_CORE_18.

However, these features are active only while LPC_EN is high, indicating

that system Main (VCC / S0) power is also good. This is “Emulated VCC”

behavior.

Name

Description

RESETI#

Power on Reset to the entire chip, externally provided.

PLTRST#

(as LRESET#)

This is the Platform Reset, used to reset internal LPC resources.

TABLE 4-2:

LPC CYCLE TYPES GENERATED

Cycle Type

Transfer Size

I/O Read

1 byte

I/O Write

1 byte

Memory Read

1 byte

Memory Write

1 byte

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