ECE1200 datasheet(35/87 Pages) MICROCHIP

35 / 87 page

 2018-2021 Microchip Technology Inc.

DS00003093C Draft-page 35

ECE1200

6.4

This section defines the Reset events that affect the register set.

6.5

Interrupts

IRQ interrupts are asserted through the Serial IRQ feature only.

The SMI# Virtual Wire may be configured to come from its dedicated Serial IRQ slot.

IRQs, and SMI# from Serial IRQ, are acknowledged only at the source, requiring no separate interaction with the

ECE1200 device.

Error exceptions may be configured to be transmitted on detection of certain LPC errors, These consist of the eSPI Vir-

tual Wires ERROR_FATAL, ERROR_NONFATAL, SMI# or SCI#. Where provided for in the eSPI protocol, the UNSUC-

CESSFUL COMPLETION response is also sent for these errors, unconditionally.

The IOCHK# (or IOCHCK#) slot in the Serial IRQ frame may also be configured to generate one of the error exceptions

above. This may be made conditional on whether an LPC transfer was in progress at the time.

Error exceptions on LPC, or IOCHK# activation, are reported in local registers, and are to be acknowledged there.

6.6

Low Power Modes

By default, the ECE1200 device operates at full power. There are the following options, which may be selected by ini-

tialization after each PLTRST reset event:

• One of the two LPC Clock pins may be disabled. This is done in the Clock Enable Register. By default, both LPC

Clock pins are enabled.

• The Serial IRQ feature may be placed in Quiet Mode. This is done in the SERIRQ Enable and Mode Register.

• A Serial IRQ clock gating mode may be selected to stop internal clocking of the Serial IRQ Master whenever it is

idle and in Quiet Mode. This is done in the SERIRQ Enable and Mode Register.

• The CLKRUN# feature may be enabled to gate either or both LPC clocks while both the LPC and Serial IRQ inter-

faces are idle. This requires the Serial IRQ Quiet Mode to be selected also. The CLKRUN# functionality is config-

ured using the Clock Enable Register, the CLKRUN Control Register and the CLKRUN Idle Clocks Register.

• Internal clocking as well as external clocking may be gated while LPC clocks are idle (typically due to the

CLKRUN# feature). This is called Light Sleep, and is enabled using the IDLE_GATEOSC bit in the Power Save

• Deep Sleep mode may be selected. In this mode, whenever the LPC and Serial IRQ features are idle and the

CLKRUN# feature has turned the LPC clocks off, the HOST_C10 Virtual Wire will be monitored from the Chipset.

If HOST_C10 is high under these conditions, the ECE1200 device will turn off its internal oscillator, entering its

Deep Sleep state. Recovery from this state takes a period of time to establish a new frequency lock against the

SUSCLK input. Deep Sleep is enabled using the VW_C10_STOPOSC bit in the Power Save Register.

To avoid the recovery delay, the FORCE_OSC_LOCK bit may also be set to ‘1’, and the tradeoff is that the clock-

ing in the device (including the LPC Clocks) will be slower than specified until the full lock is achieved.

Name

Description

PLTRST

Activation of the PLTRST# input pin by the Chipset. This is a CPU Reset,

also called “PCI Reset”. This same signal goes from the Chipset, in

parallel, to LPC devices as “LRESET#.

eSPI_RESET

Activation of the eSPI_RESET# input pin by the Chipset. This happens

on every Power On Reset of this chip, and also on certain error

conditions detected by the Chipset that do not remove power to the

device.

This reset state also activates the PLTRST reset.

RESETI

Reset In: Power On Reset to the device, signaled by activation of the

RESETI# input pin low. This signal comes to both the ECE1200 device

and the Chipset from the system as the RSMRST# signal.

This signal resets all the registers and logic in this block to its default

state, and also activates the eSPI_RESET and PLTRST resets.

ECE1200 Datasheet(PDF) 35 Page - Microchip Technology

ECE1200 Datasheet(HTML) 35 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87

Datasheet Download

Link URL