ECE1200 datasheet(52/87 Pages) MICROCHIP

52 / 87 page

ECE1200

DS00003093C Draft-page 52

 2018-2021 Microchip Technology Inc.

6.11.1

CLOCK ENABLE REGISTER

F5h

Error Cycle Address 1 Register

F6h

Error Cycle Address 2 Register

F7h

Error Cycle Address 3 Register

F8h

Error Cycle Attributes Register

F9h -- FFh

Reserved

Index

38h of Logical Device 01h

Bits

Description

Type

Default

Reset Event

7:4 Reserved

3 CLKRUN_CTL_EN_1

‘1’ = LPC_CLK1 pin may be turned off by CLKRUN#.

‘0’ = LPC_CLK1 pin is free-running. (default)

This bit is lockable in the Clock Control Lock Register.

R/W

PLTRST

2 CLKRUN_CTL_EN_0

‘1’ = LPC_CLK0 pin may be turned off by CLKRUN#.

‘0’ = LPC_CLK1 pin is free-running. (default)

This bit is lockable in the Clock Control Lock Register.

R/W

PLTRST

1 CLK1_EN

‘1’ = LPC_CLK1 pin may present LPC clocks. (default)

‘0’ = LPC_CLK1 pin is held low.

This bit is lockable in the Clock Control Lock Register.

R/W

PLTRST

0 CLK0_EN

‘1’ = LPC_CLK0 pin may present LPC clocks. (default)

‘0’ = LPC_CLK0 pin is held low.

This bit is lockable in the Clock Control Lock Register.

R/W

PLTRST

TABLE 6-4:

LPC REGISTER SUMMARY (CONTINUED)

Index

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