ECE1200 datasheet(4/87 Pages) MICROCHIP

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ECE1200

DS00003093C Draft-page 4

 2018-2021 Microchip Technology Inc.

1.0

GENERAL DESCRIPTION

The ECE1200 is a device designed to implement a Bridge function from an eSPI-configured Intel Chipset to a legacy

downstream system, providing Master interfaces for an LPC bus, Serial IRQ and CLKRUN# features.

The ECE1200 is directly powered by two Suspend (S5) supply planes, at 3.3V and 1.8V nominal. The 1.8V supply is

provided on two sets of pins: VTR_18 for I/O pins, and VTR_18_CORE for internal logic. The 3.3V supply VTR_33 is

for 3.3V I/O pins only.

The ECE1200 senses a Runtime power plane (VCC) using the pin LPC_EN, which is intended to come from the

PCH_PWROK signal supplied from the system. It uses this to emulate VCC-powered functionality on the appropriate

pins in order to avoid backdrive in the system.

TABLE 1-1:

GENERAL TERMINOLOGY

Term

Definition

System Host, or Host Chipset

Refers to the complex of the System CPU and surrounding elements, from

which originates the I/O and Memory traffic to the ECE1200 over the eSPI

Interface.

PCH

The specific element of the Host Chipset that connects to the ECE1200 from

the Host side, serving as the Master in the eSPI protocol, and controlling the

pins that serve as Host-side sideband signals to the ECE1200.

eSPI Config

Registers

Peripheral Channel

Virtual Wire

Channel

PnP Config. Portal

(INDEX / DATA)

IRQs,

Slots

ECE1200

LPC Master

SIRQ

Master

Minimal

Fabric

Handshake

Support HW

CLKRUN#

Master

CLKRUN#

LPC

Clock

(x2)

SERIRQ

LFRAME#,

LAD[3:0]

LPC Bus and Legacy

Support to Peripherals

Subset

eSPI Bus Slave Controller

Internal

Handshakes

eSPI Bus from Host

Internal

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