ECE1200 datasheet(23/87 Pages) MICROCHIP

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DS00003093C Draft-page 23

ECE1200

4.6

LPC Clock Run Control CLKRUN#

The CLKRUN# pin is used to indicate the status of the LPC Clock(s) as well as to request that stopped clocks be

restarted. The standard for CLKRUN# operation is in the document PCI Mobile Design Guide Rev 1.0.

There is only one CLKRUN# control, but it can be associated with either or both of the LPC Clock pins. A disabled Clock

is not affected by CLKRUN#, and remains disabled.

CLKRUN# Support is off by default, meaning that CLKRUN# is driven permanently low and LPC clocks are not gated.

This remains the initial state of CLKRUN# by default when the feature is enabled as well. If the Serial IRQ feature is in

Quiet Mode and idle, and the LPC bus has been idle for a defined period of time, CLKRUN# will be driven high by the

ECE1200, and then parked high using an external pull-up resistor. Any LPC Slave device that requires clocks still to be

running will pull CLKRUN# back low itself, and clocks will then continue uninterrupted. If however no Slave device pulls

CLKRUN# low, then the ECE1200 will stop the LPC clocks, holding them low.

Once clocks are off, activating CLKRUN# low will re-start them. This may happen by Slave device action, or by the

ECE1200 internally upon detecting a request for LPC traffic from the Host Chipset.

When clocks are stopped by CLKRUN# activity, other power saving modes may be engaged. See Section 6.6, "Low

Power Modes," on page 35 and Section 3.7, "Chip Power Management Features," on page 19.

4.6.1

ENABLING THE CLKRUN# FUNCTION

See Section 6.8.6, "Set Up Optional CLKRUN# Clock Gating," on page 38.

4.7

Serial IRQ

The ECE1200 device supports Serial IRQ as the Master controller, adhering to the Serial IRQ Specification for PCI Sys-

tems Version 6.0. Both Continuous Mode and Quiet Mode operation are supported. The full 21-slot frame format is pre-

sented, as has been common practice in LPC-based Southbridge devices.

Serial IRQ inputs are bridged to the equivalent eSPI Virtual Wire traffic. See Section 6.8.4, "Set Up Serial IRQ," on

page 37 for the detail and programmable options of the Serial IRQ feature. The Serial IRQ Master supports the following

serial inputs:

Legacy Interrupts:

•IRQ1

• IRQ[3:7]

• IRQ[9:12]

• IRQ[14:15]

PCI-Derived Interrupts, mappable to selected IRQ levels, including those above IRQ15:

•INTA#

•INTB#

•INTC#

•INTD#

Discrete signals:

•SMI#

• IOCHCK# (IOCHK#)

Other inputs are considered deprecated vestiges according to common practice, and are ignored.

The SMI# input on Serial IRQ is considered a signal from downstream sources, and is not captured in the ECE1200

internal register set. Polling for it in the internal register set will fail, and it will appear only in the LPC source device.

The IOCHCK# (IOCHK#) input is treated as an error condition, and three situations may be detected

The IOCHK Non-Posted Error Handling Register, Section 6.9.5, on page 41 defines the action to be taken if the

IOCHK# input is activated during the Wait phase of a Non-Posted LPC transfer (I/O Read or Write, or Memory Read).

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