ECE1200 datasheet(30/87 Pages) MICROCHIP

30 / 87 page

ECE1200

DS00003093C Draft-page 30

 2018-2021 Microchip Technology Inc.

5.8

eSPI Configuration Registers

The eSPI Configuration Register Set is only accessible using the low-level eSPI protocol commands

GET_CONFIGURATION and SET_CONFIGURATION. These are typically issued only by Chipset hardware state

machines, as directed by its own Soft-Straps, for initialization of eSPI communication parameters. These commands

include a Location field in order to designate which register is being accessed, but this Location does not reside within

the Memory or I/O space visible to CPU software.

These registers are accessible to Host software using a specialized portal in the PCH. However, accessing them is nei-

ther required nor recommended, even during BIOS POST. They are shown here only to support interpretation of eSPI

traffic for debug. See Intel’s specifications (Section 5.2) for full detail of their content and usage.

Note that the ECE1200 does not enforce a clock speed limit using these registers. It is designed to operate at a maxi-

mum frequency of 50MHz, and this is what must be declared in the Chipset’s Soft-Strap settings for eSPI communication

with this device. Any additional eSPI Slave may have its own frequency setting, including 66MHz, and its traffic will have

no effect on this device.

TABLE 5-4:

VIRTUAL WIRES IMPLEMENTED

IDX

Dir

Bit 3

Bit 2

Bit 1

Bit 0

Defaults

Reset Domain

SLP_S5#

SLP_S4#

SLP_S3#

x000

eSPI_RESET#

XOOB_RST_

WARN

PLTRST#

SUS_STAT#

x000

eSPI_RESET#

PME#

WAKE#

OOB_RST_

ACK

11x0

eSPI_RESET#

SLAVE_BOOT_

LOAD_STATUS

ERROR_

NONFATAL

ERROR_

FATAL

SLAVE_BOOT_

LOAD_DONE

0000

eSPI_RESET#

HOST_RST_

ACK

RCIN#

SMI#

SCI#

0111

PLTRST#

HOST_RST_

WARN

xxx0

PLTRST#

40h

RFU

SUS_ACK#

xx00

eSPI_RESET#

41h

SLP_A#

SUS_PWRDN_

ACK

SUS_WARN#

0x00

eSPI_RESET#

42h

SLP_WLAN#

SLP_LAN#

xx00

eSPI_RESET#

43h

(“Generic” Down)

0000

eSPI_RESET#

44h

(“Generic” Down)

0000

eSPI_RESET#

45h

(“Generic” Up from Primary Slave CS0#)

0000

eSPI_RESET#

46h

(“Generic” Up from Primary Slave CS0#)

0000

eSPI_RESET#

47h

HOST_C10

xxx0

PLTRST#

48h

(“Generic” Up from Secondary Slave CS1#)

0000

eSPI_RESET#

49h

(“Generic” Up from Secondary Slave CS1#)

0000

eSPI_RESET#

4Ah

XRFU

xx0x

eSPI_RESET#

Color Key:

No Shading:

Implemented

and used

regardless of

BOOT_DONE

pin state

Yellow:

Sent Up only if

BOOT_DONE

pin is high

Orange:

Sent up as

‘1’ if

BOOT_DONE

pin is high.

Gray:

Not

implemented.

X = Undefined

by eSPI spec

Blue:

Generated internally.

Sent Up as the Virtual Wire

if BOOT_DONE == 1

or presented on the physical

pin if BOOT_DONE == 0

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