ECE1200 datasheet(77/87 Pages) MICROCHIP

77 / 87 page

 2018-2021 Microchip Technology Inc.

DS00003093C Draft-page 77

ECE1200

9.7.7

ENTRY INTO S0IX STATE (CONNECTED STANDBY, C10)

FIGURE 9-7:

ENTRY INTO S0IX STATE (CONNECTED STANDBY, C10)

LPC_EN

(pin in)

3.3V

SUS_STAT#

(VWire Down

to pin out)

3.3V

LAD[3:0],

SERIRQ

3.3V

Running

3.3V

CLKRUN#

System must make PLTRST# fall first.

Idle

Running

SUSCLK

32KHz

3.3V

LPC Clock Gates

3.3V

Running

HOST_C10

(VWire Down)

on PLTRST#

reset domain

Oscillator Enable

(Internal)

CLKRUN# high

period: stop clocks.

Idle period:

set CLKRUN# high.

HOST_RESET_WARN

(VWire Down)

PLTRST#

(pin in)

3.3V

Not inhibited from forcing Oscillator On or restarting it if pulled low. Mechanism:

Will both reset HOST_C10 and start up LPC clocks by resetting registers.

Running

48MHz

Oscillator

(Internal)

Low = Both LPC clocks off,

and neither free-running

LPC Bus and SERIRQ are required to be already idle, and clocks off.

LFRAME#

3.3V

Running

Idle

Low = LPC Clocks Off

and HOST_C10 high.

Off, and No Lock.

Other signals, (FYI)

S0ix

(Rising would have awakened device by eSPI activity.)

(Falling would have awakened device by eSPI activity.)

Combinational

May rise before or

after LPC clock cutoff.

ECE1200 Datasheet(PDF) 77 Page - Microchip Technology

ECE1200 Datasheet(HTML) 77 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87

Datasheet Download

Link URL