ECE1200 datasheet(55/87 Pages) MICROCHIP

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DS00003093C Draft-page 55

ECE1200

6.11.6

SERIRQ EXCEPTION ENABLES REGISTER

6.11.7

SERIRQ CLOCKING REGISTER

Index

F0h of Logical Device 01h

Bits

Description

Type

Default

Reset Event

7:6 Reserved

00b

5 IOCHK_N_SERIRQ_EN_LOCK

‘1’ = The IOCHK_N_SERIRQ_EN bit in this register is locked

Read-Only in its written state. The ‘1’ value written here also

remains, read-only, until the next reset event.

‘0’ = The IOCHK_N_SERIRQ_EN bit is Read/Write. (default)

R/W/L

PLTRST

4 SMI_N_SERIRQ_EN_LOCK

‘1’ = The SMI_N_SERIRQ_EN bit in this register is locked

Read-Only in its written state. The ‘1’ value written here also

remains, read-only, until the next reset event.

‘0’ = The SMI_N_SERIRQ_EN bit is Read/Write. (default)

R/W/L

PLTRST

3:2 Reserved

00b

1 IOCHK_N_SERIRQ_EN

‘1’ = The IOCHK# slot (Slot 17) in the SERIRQ frame is sam-

pled and allowed to propagate to the eSPI interface.

‘0’ = The IOCHK# slot does not propagate. (default)

R/W/L

PLTRST

0 SMI_N_SERIRQ_EN

‘1’ = The SMI# slot (Slot 3) in the SERIRQ frame is sampled

and allowed to propagate to the eSPI interface as the SMI# Vir-

tual Wire.

‘0’ = The SMI# slot does not propagate. (default)

R/W/L

PLTRST

Index

F1h of Logical Device 01h

Bits

Description

Type

Default

Reset Event

7:1 Reserved

00h

0 SERIRQ CLK_GATE_CTL

‘1’ = Enables internal clocking at all times to the Serial IRQ cir-

cuits. (default)

‘0’ = Allows internal clocking to be shut off to Serial IRQ circuits

when idle.

R/W

PLTRST

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