R5F72115D160FPV datasheet(347/1228 Pages) RENESAS

347 / 1228 page

Section 9 Direct Memory Access Controller (DMAC)

Rev. 2.00 May. 08, 2008 Page 323 of 1200

REJ09B0344-0200

Bit

Bit Name

Initial

Value

R/W

Description

DME

R/W

DMA Master Enable

Enables or disables DMA transfer on all channels. If

the DME bit and DE bit in CHCR are set to 1, DMA

transfer is enabled.

However, transfer is enabled only when the TE bit in

CHCR of the transfer corresponding channel, the NMIF

bit in DMAOR, and the AE bit are all cleared to 0.

Clearing the DME bit to 0 can terminate the DMA

transfer on all channels.

0: DMA transfer is disabled on all channels

1: DMA transfer is enabled on all channels

Note:

Only 0 can be written to clear the flag after 1 is read.

If the priority mode bits are modified after a DMA transfer, the channel priority is initialized. If

fixed mode 2 is specified, the channel priority is specified as CH0 > CH4 > CH1 > CH5 > CH2 >

CH6 > CH3 > CH7. If fixed mode 1 is specified, the channel priority is specified as CH0 > CH1 >

CH2 > CH3 > CH4 > CH5 > CH6 > CH7. If round-robin mode is specified, the transfer end

channel is reset.

Table 9.3 show the priority change in each mode (modes 0 to 2) specified by the priority mode

bits. In each priority mode, the channel priority to accept the next transfer request may change in

up to three ways according to the transfer end channel.

For example, when the transfer end channel is channel 1, the priority of the channel to accept the

next transfer request is specified as CH2 > CH3 > CH0 >CH1 > CH4 > CH5 > CH6 > CH7. When

the transfer end channel is any one of the channels 4 to 7, round-robin will not be applied and the

priority level is not changed at the end of transfer in the channels 4 to 7.

The DMAC internal operation for an address error is as follows:

• No address error: Read (source to DMAC) → Write (DMAC to destination)

• Address error in source address: Nop → Nop

• Address error in destination address: Read → Nop

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