R5F72115D160FPV datasheet(350/1228 Pages) RENESAS

350 / 1228 page

Section 9 Direct Memory Access Controller (DMAC)

Rev. 2.00 May. 08, 2008 Page 326 of 1200

REJ09B0344-0200

Transfer requests from the various modules specify MID and RID as shown in table 9.4.

Table 9.4

DMARS Settings

Peripheral Module

Setting Value for One

Channel ({MID, RID})

MID

RID

Function

SCIF_0 transmitter

H'81

B'01

Transmit

SCIF_0 receiver

H'82

B'100000

B'10

Receive

SCIF_1 transmitter

H'85

B'01

Transmit

SCIF_1 receiver

H'86

B'100001

B'10

Receive

SCIF_2 transmitter

H'89

B'01

Transmit

SCIF_2 receiver

H'8A

B'100010

B'10

Receive

SCIF_3 transmitter

H'8D

B'01

Transmit

SCIF_3 receiver

H'8E

B'100011

B'10

Receive

IIC3 transmitter

H'A1

B'01

Transmit

IIC3 receiver

H'A2

B'101000

B'10

Receive

A/D converter

H'B3

B'101100

B'11

⎯

MTU2_0

H'E3

B'111000

B'11

⎯

MTU2_1

H'E7

B'111001

B'11

⎯

MTU2_2

H'EB

B'111010

B'11

⎯

MTU2_3

H'EF

B'111011

B'11

⎯

MTU2_4

H'F3

B'111100

B'11

⎯

CMT_0

H'FB

B'111110

B'11

⎯

CMT_1

H'FF

B'111111

B'11

⎯

When MID or RID other than the values listed in table 9.4 is set, the operation of this LSI is not

guaranteed. The transfer request from DMARS is valid only when the resource select bits

(RS[3:0]) in CHCR0 to CHCR7 have been set to B'1000. Otherwise, even if DMARS has been set,

the transfer request source is not accepted.

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