R5F72115D160FPV datasheet(352/1228 Pages) RENESAS

352 / 1228 page

Section 9 Direct Memory Access Controller (DMAC)

Rev. 2.00 May. 08, 2008 Page 328 of 1200

REJ09B0344-0200

Start

Initial settings

(SAR, DAR, DMATCR, CHCR,

DMAOR, DMARS)

DE, DME = 1 and

NMIF, AE, TE = 0?

Yes

Transfer request

occurs?*1

Transfer (one transfer unit);

DMATCR – 1

→ DMATCR,

SAR and DAR updated

DMATCR = 0?

Yes

DEI interrupt request

(when IE = 1)

For a request from an

on-chip peripheral module,

the transfer acknowledge signal

is sent to the module.

When reload function is enabled,

RSAR

→ SAR, RDAR → DAR,

and RDMATCR

→ DMATCR

TE = 1

NMIF = 1

or AE = 1 or DE = 0

or DME = 0?

NMIF = 1

or AE = 1 or DE = 0

or DME = 0?

Transfer end

Transfer terminated

Normal end

Bus mode,

transfer request mode,

DREQ detection system

Yes

DMATCR=1/2 ?

HEI interrupt request

(when HE = 1)

HE=1

When the TC bit in CHCR is 0, or

for a request from an on-chip peripheral

module, the transfer acknowledge

signal is sent to the module.

Notes: 1. In auto-request mode, transfer begins when the NMIF, AE, and TE bits are cleared to 0 and the

DE and DME bits are set to 1.

2. DREQ level detection in burst mode (external request) or cycle steal mode.

3. DREQ edge detection in burst mode (external request), or auto request mode in burst mode.

Figure 9.2 DMA Transfer Flowchart

R5F72115D160FPV Datasheet(PDF) 352 Page - Renesas Technology Corp

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