R5F72115D160FPV datasheet(355/1228 Pages) RENESAS

355 / 1228 page

Section 9 Direct Memory Access Controller (DMAC)

Rev. 2.00 May. 08, 2008 Page 331 of 1200

REJ09B0344-0200

(3)

On-Chip Peripheral Module Request

In this mode, the transfer is performed in response to the DMA transfer request signal from an on-

chip peripheral module.

DMA transfer request signals from on-chip peripheral modules to the DMAC include transmit

data empty and receive data full requests from the SCIF, A/D conversion end request from the

A/D converter, compare match request from the CMT, and data transfer requests from the IIC3

and MTU2.

When a transfer request signal is sent in on-chip peripheral module request mode while DMA

transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, and NMIF = 0), DMA transfer is

performed.

When the transmit data empty from the SCIF is selected, specify the transfer destination as the

corresponding SCIF transmit data register. Likewise, when the receive data full from the SCIF is

selected, specify the transfer source as the corresponding SCIF receive data register. When a

transfer request is made by the A/D converter, the transfer source must be the A/D data register

(ADDR). When the IIC3 transmit is selected as the transfer request, the transfer destination must

be ICDRT; when the IIC3 reception is selected as the transfer request, the transfer source must be

ICDRR. Any address can be specified for data transfer source and destination when a transfer

request is sent from the CMT or MTU2.

R5F72115D160FPV Datasheet(PDF) 355 Page - Renesas Technology Corp