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R5F72115D160FPV Datasheet(PDF) 353 Page - Renesas Technology Corp

Part # R5F72115D160FPV
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family
PDF  1228 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F72115D160FPV Datasheet(HTML) 353 Page - Renesas Technology Corp

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Section 9 Direct Memory Access Controller (DMAC)
Rev. 2.00 May. 08, 2008 Page 329 of 1200
REJ09B0344-0200
9.4.2
DMA Transfer Requests
DMA transfer requests are basically generated in either the data transfer source or destination, but
they can also be generated in external devices and on-chip peripheral modules that are neither the
transfer source nor destination.
Transfers can be requested in three modes: auto request, external request, and on-chip peripheral
module request. The request mode is selected by the RS[3:0] bits in CHCR_0 to CHCR_7 and
DMARS0 to DMARS3.
(1)
Auto-Request Mode
When there is no transfer request signal from an external source, as in a memory-to-memory
transfer or a transfer between memory and an on-chip peripheral module unable to request a
transfer, auto-request mode allows the DMAC to automatically generate a transfer request signal
internally. When the DE bits in CHCR_0 to CHCR_7 and the DME bit in DMAOR are set to 1,
the transfer begins so long as the TE bits in CHCR_0 to CHCR_7, and the AE and NMIF bits in
DMAOR are 0.
(2)
External Request Mode
In this mode a transfer is performed at the request signals (DREQ0 to DREQ3) of an external
device. Choose one of the modes shown in table 9.5 according to the application system. When the
DMA transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0), DMA transfer is
performed upon a request at the DREQ input.
Table 9.5
Selecting External Request Modes with the RS Bits
RS[3] RS[2] RS[1] RS[0] Address Mode
Transfer Source
Transfer
Destination
0
0
0
0
Dual address mode
Any
Any
0
0
1
0
Single address mode External memory,
memory-mapped
external device
External device with
DACK
1
External device with
DACK
External memory,
memory-mapped
external device
Choose to detect DREQ by either the edge or level of the signal input with the DL and DS bits in
CHCR_0 to CHCR_3 as shown in table 9.6. The source of the transfer request does not have to be
the data transfer source or destination.



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