R5F72115D160FPV datasheet(351/1228 Pages) RENESAS

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Section 9 Direct Memory Access Controller (DMAC)

Rev. 2.00 May. 08, 2008 Page 327 of 1200

REJ09B0344-0200

9.4

Operation

When there is a DMA transfer request, the DMAC starts the transfer according to the

predetermined channel priority order; when the transfer end conditions are satisfied, it ends the

transfer. Transfers can be requested in three modes: auto request, external request, and on-chip

peripheral module request. In bus mode, burst mode or cycle steal mode can be selected.

9.4.1

Transfer Flow

After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA

transfer count registers (DMATCR), DMA channel control registers (CHCR), DMA operation

conditions, the DMAC transfers data according to the following procedure:

1. Checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0)

2. When a transfer request comes and transfer is enabled, the DMAC transfers one transfer unit of

data (depending on the TS0 and TS1 settings). For an auto request, the transfer begins

automatically when the DE bit and DME bit are set to 1. The DMATCR value will be

decremented by 1 for each transfer. The actual transfer flows vary by address mode and bus

mode.

3. When half of the specified transfer count is exceeded (when DMATCR reaches half of the

initial value), an HEI interrupt is sent to the CPU if the HIE bit in CHCR is set to 1.

4. When transfer has been completed for the specified count (when DMATCR reaches 0), the

transfer ends normally. If the IE bit in CHCR is set to 1 at this time, a DEI interrupt is sent to

the CPU.

5. When an address error in the DMAC or an NMI interrupt is generated, the transfer is

terminated. Transfers are also terminated when the DE bit in CHCR or the DME bit in

DMAOR is cleared to 0.

Figure 9.2 is a flowchart of this procedure.

R5F72115D160FPV Datasheet(PDF) 351 Page - Renesas Technology Corp