R5F72115D160FPV datasheet(356/1228 Pages) RENESAS

356 / 1228 page

Section 9 Direct Memory Access Controller (DMAC)

Rev. 2.00 May. 08, 2008 Page 332 of 1200

REJ09B0344-0200

Table 9.8

Selecting On-Chip Peripheral Module Request Modes with RS3 to RS0 Bits

CHCR

DMARS

RS[3:0] MID

RID

DMA Transfer

Request

Source

DMA Transfer

Request Signal

Transfer

Source

Transfer

Destination

Bus

Mode

SCIF_0 transmit TXI0 (transmit FIFO data empty)

Any

SCFTDR_0

100000

SCIF_0 receive

RXI0 (receive FIFO data full)

SCFRDR_0 Any

SCIF_1 transmit TXI1 (transmit FIFO data empty)

Any

SCFTDR_1

100001

SCIF_1 receive

RXI1 (receive FIFO data full)

SCFRDR_1 Any

SCIF_2 transmit TXI2 (transmit FIFO data empty)

Any

SCFTDR_2

100010

SCIF_2 receive

RXI2 (receive FIFO data full)

SCFRDR_2 Any

SCIF_3 transmit TXI3 (transmit FIFO data empty)

Any

SCFTDR_3

100011

SCIF_3 receive

RXI3 (receive FIFO data full)

SCFRDR_3 Any

Cycle

steal

IIC3 transmit

TXI (transmit data empty)

Any

ICDRT

101000

IIC3 receive

RXI (receive data full)

ICDRR

Any

Cycle

steal

101100 11

A/D converter

ADI (A/D conversion end)

ADDR

Any

Cycle

steal

111000 11

MTU2_0

TGI0A

Any

111001 11

MTU2_1

TGI1A

Any

111010 11

MTU2_2

TGI2A

Any

111011 11

MTU2_3

TGI3A

Any

111100 11

MTU2_4

TGI4A

Any

Cycle

steal or

burst

111110 11

CMT_0

Compare match 0

Any

1000

111111 11

CMT_1

Compare match 1

Any

Cycle

steal or

burst

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