R5F72115D160FPV datasheet(427/1228 Pages) RENESAS

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Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 2.00 May. 08, 2008 Page 403 of 1200

REJ09B0344-0200

10.3.8

Timer Input Capture Control Register (TICCR)

TICCR is an 8-bit readable/writable register that specifies input capture conditions when TCNT_1

and TCNT_2 are cascaded. The MTU2 has one TICCR in channel 1.

Bit:

Initial value:

R/W:

7654321

00000000

R/W

I2BE

I2AE

I1BE

I1AE

Bit

Bit Name

Initial

Value

R/W

Description

7 to 4

—

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

I2BE

R/W

Input Capture Enable

Specifies whether to include the TIOC2B pin in the

TGRB_1 input capture conditions.

0: Does not include the TIOC2B pin in the TGRB_1

input capture conditions

1: Includes the TIOC2B pin in the TGRB_1 input

capture conditions

I2AE

R/W

Input Capture Enable

Specifies whether to include the TIOC2A pin in the

TGRA_1 input capture conditions.

0: Does not include the TIOC2A pin in the TGRA_1

input capture conditions

1: Includes the TIOC2A pin in the TGRA_1 input

capture conditions

I1BE

R/W

Input Capture Enable

Specifies whether to include the TIOC1B pin in the

TGRB_2 input capture conditions.

0: Does not include the TIOC1B pin in the TGRB_2

input capture conditions

1: Includes the TIOC1B pin in the TGRB_2 input

capture conditions

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