R5F72115D160FPV datasheet(428/1228 Pages) RENESAS

428 / 1228 page

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 2.00 May. 08, 2008 Page 404 of 1200

REJ09B0344-0200

Bit

Bit Name

Initial

Value

R/W

Description

I1AE

R/W

Input Capture Enable

Specifies whether to include the TIOC1A pin in the

TGRA_2 input capture conditions.

0: Does not include the TIOC1A pin in the TGRA_2

input capture conditions

1: Includes the TIOC1A pin in the TGRA_2 input

capture conditions

10.3.9

Timer Synchronous Clear Register (TSYCR)

TSYCR is an 8-bit readable/writable register that specifies conditions for clearing TCNT_3 and

TCNT_4 in the MTU2S in synchronization with the MTU2. The MTU2S has one TSYCR in

channel 3 but the MTU2 has no TSYCR.

Bit:

Initial value:

R/W:

7654321

00000000

R/W

CE0A

CE0B

CE0C

CE0D

CE1A

CE1B

CE2A

CE2B

Bit

Bit Name

Initial

Value

R/W

Description

CE0A

R/W

Clear Enable 0A

Enables or disables counter clearing when the TGFA

flag of TSR_0 in the MTU2 is set.

0: Disables counter clearing by the TGFA flag in TSR_0

1: Enables counter clearing by the TGFA flag in TSR_0

CE0B

R/W

Clear Enable 0B

Enables or disables counter clearing when the TGFB

flag of TSR_0 in the MTU2 is set.

0: Disables counter clearing by the TGFB flag in TSR_0

1: Enables counter clearing by the TGFB flag in TSR_0

R5F72115D160FPV Datasheet(PDF) 428 Page - Renesas Technology Corp

R5F72115D160FPV Datasheet(HTML) 428 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL