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R5F72115D160FPV Datasheet(PDF) 429 Page - Renesas Technology Corp

Part # R5F72115D160FPV
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family
PDF  1228 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F72115D160FPV Datasheet(HTML) 429 Page - Renesas Technology Corp

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Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
Rev. 2.00 May. 08, 2008 Page 405 of 1200
REJ09B0344-0200
Bit
Bit Name
Initial
Value
R/W
Description
5
CE0C
0
R/W
Clear Enable 0C
Enables or disables counter clearing when the TGFC
flag of TSR_0 in the MTU2 is set.
0: Disables counter clearing by the TGFC flag in TSR_0
1: Enables counter clearing by the TGFC flag in TSR_0
4
CE0D
0
R/W
Clear Enable 0D
Enables or disables counter clearing when the TGFD
flag of TSR_0 in the MTU2 is set.
0: Disables counter clearing by the TGFD flag in TSR_0
1: Enables counter clearing by the TGFD flag in TSR_0
3
CE1A
0
R/W
Clear Enable 1A
Enables or disables counter clearing when the TGFA
flag of TSR_1 in the MTU2 is set.
0: Disables counter clearing by the TGFA flag in TSR_1
1: Enables counter clearing by the TGFA flag in TSR_1
2
CE1B
0
R/W
Clear Enable 1B
Enables or disables counter clearing when the TGFB
flag of TSR_1 in the MTU2 is set.
0: Disables counter clearing by the TGFB flag in TSR_1
1: Enables counter clearing by the TGFB flag in TSR_1
1
CE2A
0
R/W
Clear Enable 2A
Enables or disables counter clearing when the TGFA
flag of TSR_2 in the MTU2 is set.
0: Disables counter clearing by the TGFA flag in TSR_2
1: Enables counter clearing by the TGFA flag in TSR_2
0
CE2B
0
R/W
Clear Enable 2B
Enables or disables counter clearing when the TGFB
flag of TSR_2 in the MTU2 is set.
0: Disables counter clearing by the TGFB flag in TSR_2
1: Enables counter clearing by the TGFB flag in TSR_2



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