R5F72115D160FPV datasheet(119/1228 Pages) RENESAS

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Section 5 Exception Handling

Rev. 2.00 May. 08, 2008 Page 95 of 1200

REJ09B0344-0200

5.6.4

General Illegal Instructions

When undefined code placed anywhere other than immediately after a delayed branch instruction

(i.e., in a delay slot) is decoded, general illegal instruction exception handling starts. The CPU

handles general illegal instructions in the same way as slot illegal instructions. Unlike processing

of slot illegal instructions, however, the program counter value stored is the start address of the

undefined code.

5.6.5

Integer Division Instructions

When an integer division instruction performs division by zero or the result of integer division

overflows, integer division instruction exception handling starts. The instructions that may become

the source of division-by-zero exception are DIVU and DIVS. The only source instruction of

overflow exception is DIVS, and overflow exception occurs only when the negative maximum

value is divided by

−1. The CPU operates as follows:

1. The exception service routine start address which corresponds to the integer division

instruction exception that occurred is fetched from the exception handling vector table.

2. The status register (SR) is saved to the stack.

3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the

integer division instruction at which the exception occurred.

4. After jumping to the address fetched from the exception handling vector table, program

execution starts. The jump that occurs is not a delayed branch.

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