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R5F72115D160FPV Datasheet(PDF) 121 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 121 Page - Renesas Technology Corp |
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121 / 1228 page  Section 5 Exception Handling Rev. 2.00 May. 08, 2008 Page 97 of 1200 REJ09B0344-0200 5.8 Stack Status after Exception Handling Ends The status of the stack after exception handling ends is as shown in table 5.11. Table 5.11 Stack Status After Exception Handling Ends Exception Type Stack Status Address error 32 bits 32 bits SR Address of instruction after executed instruction SP Interrupt 32 bits 32 bits SR Address of instruction after executed instruction SP Register bank error (overflow) 32 bits 32 bits SR Address of instruction after executed instruction SP Register bank error (underflow) 32 bits 32 bits SR Start address of relevant RESBANK instruction SP Trap instruction 32 bits 32 bits SR Address of instruction after TRAPA instruction SP Slot illegal instruction 32 bits 32 bits SR Jump destination address of delayed branch instruction SP |
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