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R5F72115D160FPV Datasheet(PDF) 120 Page - Renesas Technology Corp

Part # R5F72115D160FPV
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family
PDF  1228 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F72115D160FPV Datasheet(HTML) 120 Page - Renesas Technology Corp

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Section 5 Exception Handling
Rev. 2.00 May. 08, 2008 Page 96 of 1200
REJ09B0344-0200
5.7
When Exception Sources Are Not Accepted
When an address error, register bank error (overflow), or interrupt is generated immediately after a
delayed branch instruction, it is sometimes not accepted immediately but stored instead, as shown
in table 5.10. When this happens, it will be accepted when an instruction that can accept the
exception is decoded.
Table 5.10
Exception Source Generation Immediately after Delayed Branch Instruction
Exception Source
Point of Occurrence
Address Error
Register Bank Error
(Overflow)
Interrupt
Immediately after a delayed
branch instruction*
Not accepted
Not accepted
Not accepted
Note:
*
Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF



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