R5F72115D160FPV datasheet(150/1228 Pages) RENESAS

Part #	R5F72115D160FPV

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family

PDF	1228 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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Section 6 Interrupt Controller (INTC)

Rev. 2.00 May. 08, 2008 Page 126 of 1200

REJ09B0344-0200

Notes: The interrupt source flag should be cleared in the interrupt handler. After clearing the

interrupt source flag, "time from occurrence of interrupt request until interrupt controller

identifies priority, compares it with mask bits in SR, and sends interrupt request signal to

CPU" shown in table 6.5 is required before the interrupt source sent to the CPU is actually

cancelled. To ensure that an interrupt request that should have been cleared is not

inadvertently accepted again, read the interrupt source flag after it has been cleared, and

then execute an RTE instruction.

* Interrupt requests that are designated as edge-sensing are held pending until the

interrupt requests are accepted. IRQ interrupts, however, can be cancelled by accessing

the IRQ interrupt request register (IRQRR). For details, see section 6.4.4, IRQ

Interrupts.

Interrupts held pending due to edge-sensing are cleared by a power-on reset.

R5F72115D160FPV Datasheet(PDF) 150 Page - Renesas Technology Corp