R5F72115D160FPV datasheet(154/1228 Pages) RENESAS

154 / 1228 page

Section 6 Interrupt Controller (INTC)

Rev. 2.00 May. 08, 2008 Page 130 of 1200

REJ09B0344-0200

Number of States

Item

NMI

User Break

H-UDI

IRQ

Peripheral

Module

Remarks

Min.

5 Icyc

2 Bcyc +

1 Pcyc +

m1 + m2

6 Icyc +

m1 + m2

5 Icyc

1 Pcyc +

m1 + m2

5 Icyc

3 Bcyc +

1 Pcyc +

m1 + m2

5 Icyc

1 Bcyc +

1 Pcyc +

m1 + m2

160-MHz operation*

1*2:

0.050 to 0.106

μs

No register

banking

Max.

6 Icyc

2 Bcyc +

1 Pcyc +

2(m1 + m2) +

7 Icyc

2(m1 + m2) +

6 Icyc

1 Pcyc +

2(m1 + m2) +

6 Icyc

3 Bcyc +

1 Pcyc +

2(m1 + m2) +

6 Icyc

1 Bcyc +

1 Pcyc +

2(m1 + m2) +

160-MHz operation*

1*2:

0.075 to 0.131

μs

Min.

⎯

5 Icyc

1 Pcyc +

m1 + m2

5 Icyc

3 Bcyc +

1 Pcyc +

m1 + m2

5 Icyc

1 Bcyc +

1 Pcyc +

m1 + m2

160-MHz operation*

1*2:

0.050 to 0.106

μs

banking

without

bank

overflow

Max.

⎯

14 Icyc

1 Pcyc +

m1 + m2

14 Icyc

3 Bcyc +

1 Pcyc +

m1 + m2

14 Icyc

1 Bcyc +

1 Pcyc +

m1 + m2

160-MHz operation*

1*2:

0.106 to 0.163

μs

Min.

⎯

5 Icyc

1 Pcyc +

m1 + m2

5 Icyc

3 Bcyc +

1 Pcyc +

m1 + m2

5 Icyc

1 Bcyc +

1 Pcyc +

m1 + m2

160-MHz operation*

1*2:

0.050 to 0.106

μs

Interrupt

response time

banking

with

bank

overflow

Max.

⎯

5 Icyc

1 Pcyc + m1 +

m2 + 19(m4)

5 Icyc

3 Bcyc +

1 Pcyc + m1 +

m2 + 19(m4)

5 Icyc

1 Bcyc +

1 Pcyc + m1 +

m2 + 19(m4)

160-MHz operation*

1*2:

0.169 to 0.225

μs

Notes: m1 to m4 are the number of states needed for the following memory accesses.

m1: Vector address read (longword read)

m2: SR save (longword write)

m3: PC save (longword write)

m4: Banked registers (R0 to R14, GBR, MACH, MACL, and PR) are restored from the

stack.

1. In the case that m1 = m2 = m3 = m4 = 1 Icyc.

2. In the case that (I

φ, Bφ, Pφ) = (160 MHz, 40 MHz, 40 MHz).

R5F72115D160FPV Datasheet(PDF) 154 Page - Renesas Technology Corp

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