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R5F72115D160FPV Datasheet(PDF) 155 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 155 Page - Renesas Technology Corp |
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155 / 1228 page  Section 6 Interrupt Controller (INTC) Rev. 2.00 May. 08, 2008 Page 131 of 1200 REJ09B0344-0200 F 2 Icyc + 3 Bcyc + 1 Pcyc 3 Icyc m1 m2 m3 3 Icyc + m1 + m2 IRQ Instruction (instruction replacing interrupt exception handling) m1: m2: m3: F: D: E: M: First instruction in interrupt exception service routine Interrupt acceptance DE E M M M FD E [Legend] Vector address read Saving of SR (stack) Saving of PC (stack) Instruction fetch. Instruction is fetched from memory in which program is stored. Instruction decoding. Fetched instruction is decoded. Instruction execution. Data operation or address calculation is performed in accordance with the result of decoding. Memory access. Memory data access is performed. Figure 6.4 Example of Pipeline Operation when IRQ Interrupt is Accepted (No Register Banking) |
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