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R5F72115D160FPV Datasheet(PDF) 157 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 157 Page - Renesas Technology Corp |
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157 / 1228 page ![]() Section 6 Interrupt Controller (INTC) Rev. 2.00 May. 08, 2008 Page 133 of 1200 REJ09B0344-0200 F 2 Icyc + 3 Bcyc + 1 Pcyc 3 Icyc + m1 + m2 m1 m2 m3 9 Icyc IRQ RESBANK instruction D EEEEEEEE E DE E M M M E F D [Legend] m1: m2: m3: Vector address read Saving of SR (stack) Saving of PC (stack) Interrupt acceptance First instruction in interrupt exception service routine Instruction (instruction replacing interrupt exception handling) Figure 6.7 Example of Pipeline Operation when Interrupt is Accepted during RESBANK Instruction Execution (Register Banking without Register Bank Overflow) F 2 Icyc + 3 Bcyc + 1 Pcyc 3 Icyc m1 m2 m3 3 Icyc + m1 + m2 IRQ DE E M M M M F D [Legend] m1: m2: m3: Vector address read Saving of SR (stack) Saving of PC (stack) Interrupt acceptance First instruction in interrupt exception service routine Instruction (instruction replacing interrupt exception handling) ... ... ... Figure 6.8 Example of Pipeline Operation when IRQ Interrupt is Accepted (Register Banking with Register Bank Overflow) |
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