EP4CE40 datasheet(128/488 Pages) ALTERA

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Chapter 6: I/O Features in Cyclone IV Devices

I/O Banks

Cyclone IV Device Handbook,

May 2013

Altera Corporation

Volume 1

When designing LVTTL/LVCMOS inputs with Cyclone IV devices, refer to the

following guidelines:

■

All pins accept input voltage (VI) up to a maximum limit (3.6 V), as stated in the

recommended operating conditions provided in the Cyclone IV Device Datasheet

chapter.

■

Whenever the input level is higher than the bank VCCIO, expect higher leakage

current.

■

The LVTTL/LVCMOS I/O standard input pins can only meet the VIH and VIL

levels according to bank voltage level.

Voltage-referenced standards are supported in an I/O bank using any number of

single-ended or differential standards, as long as they use the same VREF and VCCIO

values. For example, if you choose to implement both SSTL-2 and SSTL-18 in your

Cyclone IV devices, I/O pins using these standards—because they require different

VREF values—must be in different banks from each other. However, the same I/O

bank can support SSTL-2 and 2.5-V LVCMOS with the VCCIO set to 2.5 V and the VREF

set to 1.25 V.

1 When using Cyclone IV devices as a receiver in 3.3-, 3.0-, or 2.5-V LVTTL/LVCMOS

systems, you are responsible for managing overshoot or undershoot to stay in the

absolute maximum ratings and the recommended operating conditions, provided in

the Cyclone IV Device Datasheet chapter.

1 The PCI clamping diode is enabled by default in the Quartus II software for input

signals with bank VCCIO at 2.5, 3.0, or 3.3 V.

High-Speed Differential Interfaces

Cyclone IV devices can send and receive data through LVDS signals. For the LVDS

transmitter and receiver, the input and output pins of Cyclone IV devices support

serialization and deserialization through internal logic.

The BLVDS extends the benefits of LVDS to multipoint applications such as

bidirectional backplanes. The loading effect and the need to terminate the bus at both

ends for multipoint applications require BLVDS to drive out a higher current than

LVDS to produce a comparable voltage swing. All the I/O banks of Cyclone IV

devices support BLVDS for user I/O pins.

The RSDS and mini-LVDS standards are derivatives of the LVDS standard. The RSDS

and mini-LVDS I/O standards are similar in electrical characteristics to LVDS, but

have a smaller voltage swing and therefore provide increased power benefits and

reduced electromagnetic interference (EMI).

The PPDS standard is the next generation of the RSDS standard introduced by

National Semiconductor Corporation. Cyclone IV devices meet the National

Semiconductor Corporation PPDS Interface Specification and support the PPDS

standard for outputs only. All the I/O banks of Cyclone IV devices support the PPDS

standard for output pins only.

The LVDS standard does not require an input reference voltage, but it does require a

100-

Ω termination resistor between the two signals at the input buffer. An external

resistor network is required on the transmitter side for the top and bottom I/O banks.

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