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Chapter 7: External Memory Interfaces in Cyclone IV Devices

7–11

Cyclone IV Devices Memory Interfaces Pin Support

May 2013

Altera Corporation

Cyclone IV Device Handbook,

Volume 1

Figure 7–6 shows the location and numbering of the DQS, DQ, or CQ# pins in I/O

banks of the Cyclone IV E device in the 144-pin EQFP and 164-pin MBGA packages.

In Cyclone IV devices, the ×9 mode uses the same DQ and DQS pins as the ×8 mode, and

one additional DQ pin that serves as a regular I/O pin in the ×8 mode. The ×18 mode

uses the same DQ and DQS pins as ×16 mode, with two additional DQ pins that serve as

regular I/O pins in the ×16 mode. Similarly, the ×36 mode uses the same DQ and DQS

pins as the ×32 mode, with four additional DQ pins that serve as regular I/O pins in

the ×32 mode. When not used as DQ or DQS pins, the memory interface pins are

available as regular I/O pins.

Optional Parity, DM, and Error Correction Coding Pins

Cyclone IV devices support parity in ×9, ×18, and ×36 modes. One parity bit is

available per eight bits of data pins. You can use any of the DQ pins for parity in

Cyclone IV devices because the parity pins are treated and configured similarly to DQ

pins.

DM pins are only required when writing to DDR2 and DDR SDRAM devices.

QDR II SRAM devices use the BWS# signal to select the byte to be written into

memory. A low signal on the DM or BWS# pin indicates the write is valid. Driving the

DM or BWS# pin high causes the memory to mask the DQ signals. Each group of DQS

and DQ signals has one DM pin. Similar to the DQ output signals, the DM signals are

clocked by the -90° shifted clock.

Figure 7–6. DQS, CQ, or CQ# Pins for Cyclone IV E Devices in the 144-Pin EQFP and 164-pin

MBGA Packages

Cyclone IV E Devices

in 144-pin EQFP and

164-pin MBGA

I/O Bank 8

I/O Bank 7

I/O Bank 4

I/O Bank 3

DQS0L/CQ1L

DQS1L/CQ1L#

DQS1R/CQ1R#

DQS0R/CQ1R

EP4CE40 Datasheet(PDF) 157 Page - Altera Corporation