EP4CE40 datasheet(170/488 Pages) ALTERA

170 / 488 page

8–6

Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices

Configuration

Cyclone IV Device Handbook,

May 2013

Altera Corporation

Volume 1

Configuration Process

This section describes Cyclone IV device configuration requirements and includes the

following topics:

■

“Power Up” on page 8–6

■

“Reset” on page 8–6

■

“Configuration” on page 8–6

■

“Configuration Error” on page 8–7

■

“Initialization” on page 8–7

■

“User Mode” on page 8–7

f For more information about the Altera® FPGA configuration cycle state machine, refer

to the Configuring Altera FPGAs chapter in volume 1 of the Configuration Handbook.

Power Up

If the device is powered up from the power-down state, VCCINT, VCCA, and VCCIO (for

the I/O banks in which the configuration and JTAG pins reside) must be powered up

to the appropriate level for the device to exit from POR.

Reset

After power up, Cyclone IV devices go through POR. POR delay depends on the MSEL

pin settings, which correspond to your configuration scheme. During POR, the device

resets, holds nSTATUS and CONF_DONE low, and tri-states all user I/O pins (for PS and

FPP configuration schemes only).

1 To tri-state the configuration bus for AS and AP configuration schemes, you must tie

nCE

high and nCONFIG low.

The user I/O pins and dual-purpose I/O pins have weak pull-up resistors, which are

always enabled (after POR) before and during configuration. When the device exits

POR, all user I/O pins continue to tri-state. While nCONFIG is low, the device is in

reset. When nCONFIG goes high, the device exits reset and releases the open-drain

nSTATUS

pin, which is then pulled high by an external 10-k

Ω pull-up resistor. After

nSTATUS

is released, the device is ready to receive configuration data and the

configuration stage starts.

f For more information about the value of the weak pull-up resistors on the I/O pins

that are on before and during configuration, refer to the Cyclone IV Device Datasheet

chapter.

Configuration

Configuration data is latched into the Cyclone IV device at each DCLK cycle. However,

the width of the data bus and the configuration time taken for each scheme are

different. After the device receives all the configuration data, the device releases the

open-drain CONF_DONE pin, which is pulled high by an external 10-k

Ω pull-up resistor.

A low-to-high transition on the CONF_DONE pin indicates that the configuration is

complete and initialization of the device can begin.

EP4CE40 Datasheet(PDF) 170 Page - Altera Corporation

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