EP4CE40 datasheet(192/488 Pages) ALTERA

192 / 488 page

8–28

Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices

Configuration

Cyclone IV Device Handbook,

May 2013

Altera Corporation

Volume 1

The nSTATUS and CONF_DONE pins on all target devices are connected together with

external pull-up resistors, as shown in Figure 8–8 on page 8–26 and Figure 8–9 on

page 8–27. These pins are open-drain bidirectional pins on the devices. When the first

device asserts nCEO (after receiving all its configuration data), it releases its CONF_DONE

pin. However, the subsequent devices in the chain keep this shared CONF_DONE line

low until they receive their configuration data. When all target devices in the chain

receive their configuration data and release CONF_DONE, the pull-up resistor drives a

high level on this line and all devices simultaneously enter initialization mode.

Guidelines for Connecting Parallel Flash to Cyclone IV E Devices for an AP

Interface

For single- and multi-device AP configuration, the board trace length and loading

between the supported parallel flash and Cyclone IV E devices must follow the

recommendations listed in Table 8–11. These recommendations also apply to an AP

configuration with multiple bus masters.

Configuring With Multiple Bus Masters

Similar to the AS configuration scheme, the AP configuration scheme supports

multiple bus masters for the parallel flash. For another master to take control of the

AP configuration bus, the master must assert nCONFIG low for at least 500 ns to reset

the master Cyclone IV E device and override the weak 10-k

Ω pull-down resistor on

the nCE pin. This resets the master Cyclone IV E device and causes it to tri-state its AP

configuration bus. The other master device then takes control of the AP configuration

bus. After the other master device is done, it releases the AP configuration bus, then

releases the nCE pin, and finally pulses nCONFIG low to restart the configuration.

In the AP configuration scheme, multiple masters share the parallel flash. Similar to

the AS configuration scheme, the bus control is negotiated by the nCE pin.

Table 8–11. Maximum Trace Length and Loading for AP Configuration

Cyclone IV E AP Pins

Maximum Board Trace Length from

Cyclone IV E Device to Flash Device

(inches)

Maximum Board Load (pF)

DCLK

DATA[15..0]

PADD[23..0]

nRESET

Flash_nCE

nOE

nAVD

nWE

I/O (1)

Note to Table 8–11:

(1) The AP configuration ignores the WAIT signal from the flash during configuration mode. However, if you are

accessing flash during user mode with user logic, you can optionally use the normal I/O to monitor the WAIT signal

from the Micron P30 or P33 flash.

EP4CE40 Datasheet(PDF) 192 Page - Altera Corporation

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