EP4CE40 datasheet(195/488 Pages) ALTERA

195 / 488 page

Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices

8–31

Configuration

May 2013

Altera Corporation

Cyclone IV Device Handbook,

Volume 1

Programming Parallel Flash Memories

Supported parallel flash memories are external non-volatile configuration devices.

They are industry standard microprocessor flash memories. For more information

about the supported families for the commodity parallel flash, refer to Table 8–10 on

page 8–22.

Cyclone IV E devices in a single- or multiple-device chain support in-system

programming of a parallel flash using the JTAG interface with the flash loader

megafunction. The board intelligent host or download cable uses the four JTAG pins

on Cyclone IV E devices to program the parallel flash in system, even if the host or

download cable cannot access the configuration pins of the parallel flash.

f For more information about using the JTAG pins on Cyclone IV E devices to program

the parallel flash in-system, refer to AN 478: Using FPGA-Based Parallel Flash Loader

(PFL) with the Quartus II Software.

In the AP configuration scheme, the default configuration boot address is 0×010000

when represented in 16-bit word addressing in the supported parallel flash memory

(Figure 8–12). In the Quartus II software, the default configuration boot address is

0×020000 because it is represented in 8-bit byte addressing. Cyclone IV E devices

configure from word address 0×010000, which is equivalent to byte address 0×020000.

1 The Quartus II software uses byte addressing for the default configuration boot

address. You must set the start address field to 0×020000.

EP4CE40 Datasheet(PDF) 195 Page - Altera Corporation