EP4CE40 datasheet(198/488 Pages) ALTERA

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8–34

Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices

Configuration

Cyclone IV Device Handbook,

May 2013

Altera Corporation

Volume 1

To ensure DCLK and DATA[0] are not left floating at the end of configuration, the

MAX II device must drive them either high or low, whichever is convenient on your

board. The DATA[0] pin is available as a user I/O pin after configuration. In the PS

scheme, the DATA[0] pin is tri-stated by default in user mode and must be driven by

the external host device. To change this default option in the Quartus II software,

select the Dual-Purpose Pins tab of the Device and Pin Options dialog box.

The configuration clock (DCLK) speed must be below the specified system frequency to

ensure correct configuration. No maximum DCLK period exists, which means you can

pause configuration by halting DCLK for an indefinite amount of time.

The external host device can also monitor CONF_DONE and INIT_DONE to ensure

successful configuration. The CONF_DONE pin must be monitored by the external device

to detect errors and to determine when programming is complete. If all configuration

data is sent, but CONF_DONE or INIT_DONE has not gone high, the external device must

reconfigure the target device.

Figure 8–14 shows how to configure multiple devices using an external host device.

This circuit is similar to the PS configuration circuit for a single device, except that

Cyclone IV devices are cascaded for multi-device configuration.

Figure 8–14. Multi-Device PS Configuration Using an External Host

Notes to Figure 8–14:

(1) The pull-up resistor must be connected to a supply that provides an acceptable input signal for all devices in the

chain. VCC must be high enough to meet the VIH specification of the I/O on the device and the external host.

(2) Connect the pull-up resistor to the VCCIO supply voltage of the I/O bank in which the nCE pin resides.

(3) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.

(4) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect the MSEL pins,

refer to Table 8–3 on page 8–8, Table 8–4 on page 8–8, and Table 8–5 on page 8–9. Connect the MSEL pins directly

to VCCA or GND.

(5) All I/O inputs must maintain a maximum AC voltage of 4.1 V. DATA[0] and DCLK must fit the maximum overshoot

outlined in Equation 8–1 on page 8–5.

External Host

(MAX II Device or

Microprocessor)

Memory

ADDR

Cyclone IV Device 1

nSTATUS

CONF_DONE

10 k



nCE

nCEO

DATA[0]

GND

VCCIO (1) VCCIO (1)

10 k



MSEL[ ]

DATA[0]

(5)

nCONFIG

DCLK

(5)

nSTATUS

CONF_DONE

nCE

nCEO

N.C. (3)

DATA[0]

(5)

nCONFIG

DCLK

(5)

VCCIO (2)

10 k



Cyclone IV Device 2

(4)

MSEL[ ]

(4)

Buffers (5)

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