UM0434 datasheet(108/390 Pages) STMICROELECTRONICS

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UM0434

Instruction model

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instruction exception. However, the vector SPFP APU supports single-precision vector (64-

bit, two 32-bit operand) instructions, and the scalar SPFP APU performs single-precision

floating-point operations using the lower 32 bits of the GPRs. These instructions are

described in

Chapter 5.10.4: Embedded vector and scalar single precision floating point

APU instructions on page 120.” Unlike the PowerPC UISA, the SPFP APUs store floating-

point values as single-precision values in true 32-bit, single-precision format rather than in a

64-bit double-precision format used with FPRs.

5.2

Unsupported instructions and instruction forms

Because the e200z3 is a 32-bit Book E core, all of the instructions defined for 64-bit

implementations of the Book E architecture are illegal on the e200z3 and cause an illegal

instruction exception type program interruption. The e200z3 core does not support the

instructions listed in

Table 100. An unimplemented instruction or floating-point-unavailable

exception is generated if the processor attempts to execute one of these instructions.

5.3

Optionally supported instructions and instruction forms

The e200z3 core optionally supports the instructions listed in

Table 101 if a cache and/or

TLB is present. An instruction exception may be generated if the processor attempts to

execute one of these instructions and the related functional block is not present, or the

specific instruction may be treated as a no-op.

5.4

Implementation-Specific instructions

Book E defines some instructions that are implementation specific.

Table 102 summarizes

the e200z3 implementation-specific instructions.

Table 100.

List of unsupported instructions

Type/Name

Mnemonics

String Instructions

lswi, lswx, stswi, stswx

Floating Point Instructions

fxxxx, lfxxxx, sfxxxx, mcrfs, mffs, mtfxxx

Device control register and Move from APID

mfapidi, mfdcrx, mtdcrx

Table 101.

List of optionally supported instructions

Type/name

Mnemonics

Unit

Cache management

instructions

dcba, dcbf, dcbi, dcbt, dcbtst, dcbst,

dcbz

icbi, icbt

Data cache/unified cache

Instruction cache/unified

cache

Cache locking instructions

dcbtls, dcbtstls, dcblc

icbtls, icblc

Data cache/unified cache

Instruction cache/unified

cache

TLB management

instructions

tlbivax, tlbre, tlbsx, tlbsync, tlbwe

TLB

DCR management

mfdcr, mtdcr

DCR

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