ADV7182ABCPZ datasheet(28/102 Pages) AD

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ADV7182A

Data Sheet

Rev. 0 | Page 28 of 102

VS_COAST_MODE[1:0]—Address 0xF9, Bits[3:2]

If no video source is connected, then this function can set the

video output standard during freerun mode.

If a valid input video source is connected to the ADV7182A and

freerun mode is forced, the VS_COAST_MODE bits are ignored.

The freerun standard is the same as the valid inputted video

standard.

Table 35. VS_COAST_MODE Function

VS_COAST_MODE

Description

00 (default)

The ADV7182A outputs in the same standard

as it did before it entered freerun mode. If no

valid standard was output before entering

freerun mode, the ADV7182A outputs a

576i, 50 Hz signal in freerun mode.

Outputs a 576i 50 Hz signal in freerun mode.

Outputs a 480i 60 Hz signal in freerun mode.

Reserved.

CLAMP OPERATION

The input video is ac-coupled into the ADV7182A, which

protects the ADV7182A from STB events. However, the dc

value of the input video must be restored. This process is

referred to as clamping the video. This section explains the

general process of clamping on the ADV7182A in both single-

ended and differential modes. This section also discusses the

different ways a user can configure clamp operation behavior.

Single-Ended CVBS Clamp Operation

The ADV7182A uses a combination of current sources and a

digital processing block for clamping, as shown in Figure 15.

The analog processing channel shown in Figure 15 is replicated

four times inside the IC. Whereas only a single channel is

required for a single-ended CVBS signal, two independent

channels are required for Y/C (SVHS) type signals, and three

independent channels are required to allow component signals

(YPrPb) to be processed.

The clamping is divided into two sections:



Clamping before the ADC (analog domain): current

sources and voltage sources.



Clamping after the ADC (digital domain): digital

processing block.

The primary task of the analog clamping circuits is to ensure

that the video signal stays within the valid 1.0 V ADC input

window so that the analog-to-digital conversion can take place.

The current sources in Figure 15 correct the dc level of the

ac-coupled input video signal before it is fed into the ADC. The

digitized data from the ADC is then fed into the video processor.

The digital fine clamp block within the video processor corrects

any remaining variation in the dc level. The video processor

also sends clamp control signals to the current sources. This

feedback loop fine tunes the current clamp operation and

compensates for any noise on the inputted video signal. This

maintains the dc level of the video signal during normal operation.

Differential CVBS Clamping Operation

The differential clamping operation works in a similar manner to

the single-ended clamping operation (see Single-Ended CVBS

Clamp Operation section). In differential mode, a coarse clamp

pulls the positive and negative video input to a common-mode

voltage, VCML (see Figure 16). The feedback loop between the

current clamps and the video processor fine tune this coarse dc

offset and make the clamping robust to noise on the video input.

Note that the current clamps are controlled within a feedback loop

between the AFE and the video processor, and the coarse clamps

are not.

Figure 15. Single-Ended Clamping Overview

Figure 16. Differential Clamping Overview

DATA PRE-

PROCESSOR

ADC

VIDEO PROCESSOR

WITH DIGITAL

FINE CLAMP

CLAMP CONTROL

DIGITAL CORE

ANALOG FRONT END (AFE)

EXTERNAL AC

COUPLING

CAPACITOR

SINGLE-ENDED

ANALOG

VIDEO INPUT

CURRENT

SOURCE

CLAMPS

ADV7182A

DATA PRE-

PROCESSOR

ADC

CURRENT

SOURCE

CLAMPS

VIDEO PROCESSOR

WITH DIGITAL

FINE CLAMP

CLAMP CONTROL

DIGITAL CORE

ANALOG FRONT END (AFE)

EXTERNAL AC

COUPLING

CAPACITOR

POSITIVE

DIFFERENTIAL ANALOG

VIDEO INPUT

NEGATIVE

DIFFERENTIAL ANALOG

VIDEO INPUT

ADV7182A

COARSE

CLAMP

COARSE

CLAMP

CURRENT

SOURCE

CLAMPS

EXTERNAL AC

COUPLING

CAPACITOR

VCML

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