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ADV7182ABCPZ Datasheet(PDF) 79 Page - Analog Devices

Part # ADV7182ABCPZ
Description  10-Bit, SDTV Video Decoder with Differential Inputs
PDF  102 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADV7182ABCPZ Datasheet(HTML) 79 Page - Analog Devices

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Data Sheet
ADV7182A
Rev. 0 | Page 79 of 102
Main Map
Bits (Shading Indicates Default
State)
Comments
Notes
Subaddress
Register
Bit Description
7
6
5
4
3
2
1
0
0x32
VS/FIELD
Control 2
Reserved
0
0
0
0
0
1
Sets to default
NEWAVMODE bit
must be set high
VSBHE
0
VSYNC signal goes high in the
middle of the line (even field)
1
VSYNC signal changes state at
the start of the line (even field)
VSBHO
0
VSYNC signal goes high in the
middle of the line (odd field)
1
VSYNC signal changes state at
the start of the line (odd field)
0x33
VS/FIELD
Control 3
Reserved
0
0
0
1
0
0
Sets to default
VSEHE
0
VSYNC signal goes low in the
middle of the line (even field)
NEWAVMODE bit
must be set high
1
VSYNC signal changes state at
the start of the line (even field)
VSEHO
0
VSYNC signal goes low in the
middle of the line (odd field)
1
VSYNC signal changes state at
the start of the line odd field
0x34
HS Position
Control 1
HSE[10:8]; HSYNC end allows
positioning of the HSYNC
output within the video line
0
0
0
HSYNC output ends HSE[10:0]
pixels after the falling edge of
HSYNC
Using HSB and HSE,
the position/length
of the output
HSYNC can be
programmed
Reserved
0
Sets to 0
HSB[10:8]; HSYNC begin allows
positioning of the HSYNC
output within the video line
0
0
0
HS output starts HSB[10:0]
pixels after the falling edge of
HSYNC
Reserved
0
Sets to 0
0x35
HS Position
Control 2
HSB[7:0]; see Address 0x34,
using HSB[10:0] and HSE[10:0],
users can program the position
and length of the HSYNC
output signal
0
0
0
0
0
0
1
0
0x36
HS Position
Control 3
HSE[7:0]; see Address 0x35
description
0
0
0
0
0
0
0
0



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