ADV7182ABCPZ datasheet(33/102 Pages) AD

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Data Sheet

ADV7182A

Rev. 0 | Page 33 of 102

GAIN OPERATION

The gain control within the ADV7182A is performed on a

purely digital basis. The input ADC supports a 10-bit range

mapped into a 1.0 V analog voltage range. Gain correction takes

place after the digitization in the form of a digital multiplier.

Advantages of this architecture over the commonly used

programmable gain amplifier (PGA) before the ADC include

the fact that the gain is completely independent of supply,

temperature, and process variations.

As shown in Figure 25, the ADV7182A can decode a video

signal as long as it fits into the ADC window. The components

for this decoding are the amplitude of the input signal and the dc

level it resides on. The dc level is set by the clamping circuitry

(see the Clamp Operation section).

If the amplitude of the analog video signal is too high, clipping

may occur, resulting in visual artifacts. The analog input range

of the ADC, together with the clamp level, determines the

maximum supported amplitude of the video signal.

Figure 23 and Figure 24 show the typical voltage divider networks

required to keep the input video signal within the allowed range of

the ADC, 0 V to 1 V. Place the circuit in Figure 23 before all the

single-ended analog inputs to the ADV7182A, and place the circuit

in Figure 24 before all the differential inputs to the ADV7182A.

Figure 23. Single-Ended Input Voltage Divider Network

Figure 24. Differential Input Voltage Divider Network

The minimum supported amplitude of the input video is

determined by the ability of the ADV7182A to retrieve horizontal

and vertical timing and to lock to the color burst, if present.

There are separate gain control units for luma and chroma data.

Both can operate independently of each other. The chroma unit,

however, can also take its gain value from the luma path.

The possible AGC modes are shown in Table 40.

Table 40. AGC Modes

Input Video Type

Luma Gain

Chroma Gain

Any

Manual gain luma

Manual gain chroma

CVBS

Dependent on

horizontal sync depth

Dependent on color

burst amplitude

taken from luma path

Peak white

Dependent on color

burst amplitude

taken from luma path

Y/C

Dependent on

horizontal sync depth

Dependent on color

burst amplitude

taken from luma path

Peak white

Dependent on color

burst amplitude

YPrPb

Dependent on

horizontal sync depth

Taken from luma path

It is possible to freeze the automatic gain control loops, which

causes the loops to stop updating and the AGC determined gain

at the time of the freeze to stay active until the loop is either

unfrozen or the gain mode of operation is changed.

The currently active gain from any of the modes can be read

back. Refer to the description of the dual function manual gain

registers, LG[11:0] luma gain and CG[11:0] chroma gain, in the

Luma Gain section and the Chroma Gain section.

Figure 25. Gain Control Overview

51Ω

24Ω

100nF

ANALOG VIDEO

INPUT

AINx of ADV7182A

AINX

ANALOG_INPUT

CVBS_1P

ANALOG_INPUT

CVBS_1N

75Ω

1.3kΩ

0.1µF

1.3kΩ

0.1µF

430Ω

ANALOG VOLTAGE RANGE SUPPORTED BY ADC

(1V RANGE FOR ADV7182A)

DATA PRE-

PROCESSOR

(DPP)

ADC

VIDEO PROCESSOR

(GAIN SELECTION ONLY)

MAXIMUM

VOLTAGE

MINIMUM

VOLTAGE

CLAMP

LEVEL

GAIN

CONTROL

ADV7182ABCPZ Datasheet(PDF) 33 Page - Analog Devices

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