ADV7182ABCPZ datasheet(23/102 Pages) AD

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Data Sheet

ADV7182A

Rev. 0 | Page 23 of 102

ACE AND DITHER PROCESSING BLOCKS

The ACE block offers improved visual detail by using an

algorithm to automatically vary the contrast levels to enhance

picture detail (see the Adaptive Contrast Enhancement section).

When enabled, the dither block converts the digital output of the

ADV7182A from 8-bit pixel data down to 6-bit pixel data. This

function makes it easier for the ADV7182A to communicate

with some LCD panels (see the Dither Function section).

SYNC PROCESSING

The ADV7182A extracts syncs embedded in the analog input

video signal. There is currently no support for external HS/VS

inputs. The sync extraction is optimized to support imperfect

video sources, such as VCRs with head switches. The actual

algorithm uses a coarse detection based on a threshold crossing,

followed by a more detailed detection using an adaptive

interpolation algorithm. The raw sync information is sent to a

line length measurement and prediction block. The output of

this information then drives the digital resampling section to

ensure that the ADV7182A outputs 720 active pixels per line.

The sync processing on the ADV7182A also includes the following

specialized postprocessing blocks that filter and condition the

raw sync information retrieved from the digitized analog video:



VSYNC processor. This block provides extra filtering of the

detected VSYNC signals to improve vertical lock.



HSYNC processor. The HSYNC processor filters incoming

HSYNCS signals corrupted by noise, providing much

improved performance for video signals with a stable time

base but poor SNR.

VERTICAL BLANK INTERVAL (VBI) DATA RECOVERY

The ADV7182A can retrieve the following information from

the input video:



Wide screen signaling (WSS).



Copy generation management system (CGMS).



Closed captioning (CCAP).



Rovi protection presence.



Teletext.

The ADV7182A is also capable of automatically detecting the

incoming video standard with respect to color subcarrier

frequency, field rate, and line rate.

The ADV7182A can configure itself to support PAL B/PAL D/

PAL I/PAL G/PAL H, PAL M, PAL N, PAL Combination N,

NTSC M/NTSC J, SECAM 50 Hz/60 Hz, NTSC 4.43, and PAL 60.

GENERAL SETUP

Video Standard Selection

The VID_SEL[3:0] bits (Address 0x02, Bits[7:4]) allow the user

to force the digital core into a specific video standard; this is not

necessary under normal circumstances. The VID_SEL[3:0] bits

default to an autodetection mode that supports PAL, NTSC,

SECAM, and variants thereof.

Autodetection of SD Modes

To guide the autodetect system of the ADV7182A, individual

enable bits are provided for each of the supported video standards.

Setting the relevant bit to 0 inhibits the standard from being

detected automatically. Instead, the system chooses the closest of

the remaining enabled standards. The results of the autodetection

block can be read back via the status registers (see the Global

Status Register section for more information).

VID_SEL[3:0], Address 0x02[7:4]

Table 22. VID_SEL Function

VID_SEL[3:0]

Description

0000 (default)

Autodetect PAL B/PAL G/PAL H/PAL I/PAL D,

NTSC J (no pedestal), SECAM

0001

Autodetect PAL B/PAL G/PAL H/PAL I/PAL D,

NTSC M (pedestal), SECAM

0010

Autodetect PAL N (pedestal), NTSC J

(no pedestal), SECAM

0011

Autodetect PAL N (pedestal), NTSC M

(pedestal), SECAM

0100

NTSC J

0101

NTSC M

0110

PAL 60

0111

NTSC 4.43

1000

PAL B/PAL G/PAL H/PAL I/PAL D

1001

PAL N = PAL B/PAL G/PAL H/PAL I/PAL D (with

pedestal)

1010

PAL M (without pedestal)

1011

PAL M

1100

PAL Combination N

1101

PAL Combination N (with pedestal)

1110

SECAM

1111

SECAM

AD_SEC525_EN, SECAM 525 Autodetect Enable—

Address 0x07, Bit 7

Setting AD_SEC525_EN to 0 (default) disables the autodetection

of a 525-line system with a SECAM style, FM modulated color

component. Setting AD_SEC525_EN to 1 enables the detection

of a SECAM style, FM modulated color component.

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