ADV7182ABCPZ datasheet(19/102 Pages) AD

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Data Sheet

ADV7182A

Rev. 0 | Page 19 of 102

VS/FIELD/SFL Sync Mux Selection

FLD_OUT_SEL[2:0]—Address 0x6B, Bits[2:0]

The FLD_OUT_SEL[2:0] bits select whether the VS/FIELD/

SFL pin outputs vertical sync, horizontal sync, field sync, data

enable (DE), or subcarrier frequency lock (SFL) signals.

Note that the VS/FIELD/SFL pin must be active for this selection

to occur. See the Tristate Output Drivers section and the

Tristate LLC Driver section.

Table 12. FLD_OUT_SEL Function

FLD_OUT_SEL[2:0]

Description

000

The VS/FIELD/SFL pin outputs horizontal

sync information.

001

The VS/FIELD/SFL pin outputs vertical sync

information.

010 (default)

The VS/FIELD/SFL pin outputs field sync

information.

011

The VS/FIELD/SFL pin outputs DE

information.

100

The VS/FIELD/SFL pin outputs SFL

information.

HS Sync Mux Selection

HS_OUT_SEL[2:0]—Address 0x6A, Bits[2:0]

The HS_OUT_SEL[2:0] bits allow the user to change the operation

of the HS pin. The HS pin is set to output horizontal sync signals as

the default. The user can also set the HS pin to output vertical

sync, field sync, DE, or SFL information.

Note that the HS pin must be active for this selection to occur

(see the Tristate Output Drivers section and the Tristate LLC Driver

section).

Table 13. HS_OUT_SEL Function

HS_OUT_SEL[2:0]

Description

000 (default)

The HS pin output horizontal sync

information.

001

The HS pin outputs vertical sync information.

010

The HS pin outputs field sync information.

011

The HS pin outputs DE information.

100

The HS pin outputs SFL information.

Drive Strength Selection (Data)

DR_STR[1:0]—Address 0xF4, Bits[5:4]

For EMC and crosstalk reasons, it may be desirable to strengthen or

weaken the drive strength of the output drivers. The DR_STR[1:0]

bits affect the drive strength for the pixel output pins (P[7:0])

and the timing pins (HS and VS/FIELD/SFL).

For more information on tristate control, see the Tristate

Output Drivers section and the Tristate LLC Driver section.

Table 14. DR_STR Function

DR_STR[1:0]

Description

Low drive strength (1×)

01 (default)

Medium low drive strength (2×)

Medium high drive strength (3×)

High drive strength (4×)

Drive Strength Selection (Clock)

DR_STR_C[1:0]—Address 0xF4, Bits[3:2]

The DR_STR_C[1:0] bits can be used to select the strength of

the clock signal output driver (LLC pin). For more information,

see the Drive Strength Selection (Data) section.

Table 15. DR_STR_C Function

DR_STR_C[1:0]

Description

Low drive strength (1×)

01 (default)

Medium low drive strength (2×)

Medium high drive strength (3×)

High drive strength (4×)

Drive Strength Selection (I2C)

DR_STR_S[1:0]—Address 0xF4, Bits[1:0]

The DR_STR_S[1:0] bits allow the user to select the strength of

the I2C signal output drivers. This affects the drive strength for

the SDA and SCL pins.

Table 16. DR_STR_S Function

DR_STR_S[1:0]

Description

Low drive strength (1×)

01 (default)

Medium low drive strength (2×)

Medium high drive strength (3×)

High drive strength (4×)

Enable Subcarrier Frequency Lock Pin

EN_SFL_PIN—Address 0x04, Bit 1

The EN_SFL_PIN bit enables the output of subcarrier lock

information (also known as genlock) from the ADV7182A core

to an encoder in a decoder/encoder back to back arrangement.

When the EN_SFL_PIN is 0 (default), the SFL output is

disabled. When EN_SFL_PIN is 1, the SFL information is

presented on the SFL pin.

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