ADV7182ABCPZ datasheet(64/102 Pages) AD

64 / 102 page

ADV7182A

Data Sheet

Rev. 0 | Page 64 of 102

I2C INTERFACE

The ADV7182A supports a 2-wire (I2C-compatible) serial

interface. Two inputs, serial data (SDATA) and serial clock

(SCLK), carry information between the ADV7182A and the

system I2C master controller. Each slave device is recognized by

a unique address. The ADV7182A I2C port allows the user to

set up and configure the decoder and to read back the captured

VBI data. The ADV7182A has four possible slave addresses for

both read and write operations, depending on the logic level of

the ALSB pin. The four unique addresses are shown in Table 92.

The ADV7182A ALSB pin controls Bit 1 of the slave address. By

altering the ALSB, it is possible to control two ADV7182As in

an application without the conflict of using the same slave

address. The LSB (Bit 0) sets either a read or write operation.

Logic 1 corresponds to a read operation, and Logic 0

corresponds to a write operation.

Table 92. I2C Address for ADV7182A

ALSB

R/W

Slave Address

Hexadecimal

Binary

0 (read)

0x40

0b’ 0100 0000

1 (write)

0x41

0b’ 0100 0001

0 (read)

0x42

0b’ 01000010

1 (write)

0x43

0b’ 0100 0011

To control the device on the bus, a specific protocol must be

followed. First, the master initiates a data transfer by establishing a

start condition, which is defined by a high to low transition on

SDATA while SCLK remains high. This indicates that an address/

data stream follows. All peripherals respond to the start condition

and shift the next eight bits (the 7-bit address plus the R/W bit).

The bits are transferred from MSB down to LSB. The peripheral

that recognizes the transmitted address responds by pulling the

data line low during the ninth clock pulse; this is known as an

acknowledge bit. All other devices withdraw from the bus at

this point and maintain an idle condition. The idle condition is

where the device monitors the SDATA and SCLK lines for the

start condition and the correct transmitted address. The R/W

bit determines the direction of the data. Logic 0 on the LSB of

the first byte means that the master writes information to the

peripheral. Logic 1 on the LSB of the first byte means that the

master reads information from the peripheral.

The ADV7182A acts as a standard slave device on the bus. The

data on the SDATA pin is eight bits long, supporting the 7-bit

address plus the R/W bit. The device has subaddresses to enable

access to the internal registers. It, therefore, interprets the first

byte as the device address and the second byte as the starting

subaddress. The subaddresses auto-increment, allowing data to

be written to or read from the starting subaddress. A data transfer

is always terminated by a stop condition. The user can also

access any unique subaddress register on a one by one basis

without updating all the registers.

Stop and start conditions can be detected at any stage during the

data transfer. If these conditions are asserted out of sequence with

normal read and write operations, they cause an immediate jump

to the idle condition. During a given SCLK high period, only issue

one start condition, one stop condition, or a single stop condition

followed by a single start condition. If an invalid subaddress is

issued, the ADV7182A does not issue an acknowledge and returns

to the idle condition.

In auto-increment mode, if the user exceeds the highest

subaddress, the following action is taken:



In read mode, the highest subaddress register contents

continue to be output until the master device issues a

no acknowledge. This indicates the end of a read. A no

acknowledge condition occurs when the SDATA line is

not pulled low on the ninth pulse.



In write mode, the data for the invalid byte is not loaded

into any subaddress register. A no acknowledge is issued by

the ADV7182A, and the device returns to the idle condition.

Figure 46. Bus Data Transfer

Figure 47. Read and Write Sequence

SDATA

SCLK

START ADDR

ACK

DATA

ACK

STOP

SUBADDRESS

1–7

R/W

WRITE

SEQUENCE

SLAVE ADDR A(S)

SUB ADDR

A(S)

DATA

A(S)

DATA

A(S) P

READ

SEQUENCE

SLAVE ADDR

A(S)

SUB ADDR

A(S) S

A(S)

DATA

A(M)

DATA

A(M) P

S = START BIT

P = STOP BIT

A(S) = ACKNOWLEDGE BY SLAVE

A(M) = ACKNOWLEDGE BY MASTER

A(S) = NO ACKNOWLEDGE BY SLAVE

A(M) = NO ACKNOWLEDGE BY MASTER

LSB = 1

LSB = 0

ADV7182ABCPZ Datasheet(PDF) 64 Page - Analog Devices

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