ADV7182ABCPZ datasheet(58/102 Pages) AD

58 / 102 page

ADV7182A

Data Sheet

Rev. 0 | Page 58 of 102

Interrupt Mask Register Details

The following bits set the interrupt mask on the signal from the

VDP VBI data slicer.

VDP_CCAPD_MSK—Address 0x50, Bit 0, Interrupt/

VDP Map

Setting VDP_CCAPD_MSK to 0 (default) masks (disables) the

interrupt on the VDP_CCAPD_Q signal.

Setting VDP_CCAPD_MSK to 1 unmasks (enables) the

interrupt on the VDP_CCAPD_Q signal.

VDP_CGMS_WSS_CHNGD_MSK—Address 0x50, Bit 2,

Interrupt/VDP Map

Setting VDP_CGMS_WSS_CHNGD_MSK to 0 (default) masks

(disables) the interrupt on the VDP_CGMS_WSS_ CHNGD_Q

signal.

Setting VDP_CGMS_WSS_CHNGD_MSK to 1 unmasks

(enables) the interrupt on the VDP_CGMS_WSS_CHNGD_Q

signal.

Interrupt Status Register Details

The following read only bits contain data detection information

from the VDP module since the status bit was last cleared or

unmasked.

VDP_CCAPD_Q—Address 0x4E, Bit 0, Interrupt/VDP Map

When VDP_CCAPD_Q is 0 (default), CCAP data is not detected.

When VDP_CCAPD_Q is 1, CCAP data is detected.

VDP_CGMS_WSS_CHNGD_Q—Address 0x4E, Bit 2,

Interrupt/VDP Map

When VDP_CGMS_WSS_CHNGD_Q is 0 (default), CGMS or

WSS data is not detected.

VDP_CGMS_WSS_CHNGD_Q is also 0 if the CGMS or WSS

data state has not changed since it was last cleared (see the

Interrupt Status Clear Register Details section).

When VDP_CGMS_WSS_CHNGD_Q is 1, CGM or WSS data

is detected.

Interrupt Status Clear Register Details

It is not necessary to write 0 to these write only bits because

they automatically reset after being set to 1 (self clearing).

VDP_CCAPD_CLR—Address 0x4F, Bit 0,

Interrupt/VDP Map

Setting VDP_CCAPD_CLR to 1 clears the VDP_CCAP_Q bit.

VDP_CGMS_WSS_CHNGD_CLR, Address 0x4F[2],

Interrupt/VDP Map

Setting VDP_CGMS_WSS_CHNGD_CLR to 1 clears the

VDP_CGMS_WSS_CHNGD_Q bit.

I2C READBACK REGISTERS

Teletext

Because teletext is a high data rate standard, the decoded bytes

are available only as ancillary data. However, a TTXT_AVL bit

is provided in I2C so that the user can check whether the VDP

has detected teletext. Note that the TTXT_AVL bit is a plain

status bit and does not use the protocol discussed in the I2C

Interface section. When teletext is detected, the TTXT_AVL bit

goes high and remains high until cleared by the TTXT_CLEAR bit.

TTXT_AVL, Teletext Detected Status—Address 0x78,

Bit 7, Interrupt/VDP Map, Read Only

When TTXT_AVL is 0, teletext is not detected.

When TTXT_AVL is 1, teletext is detected.

TTXT_CLEAR, Teletext Clear—Address 0x78, Bit 7,

Interrupt/VDP Map, Write Only

Setting TTXT_CLEAR to 1 clears the TTXT_AVL bit.

WST Packet Decoding

For WST only, the VDP decodes the magazine and row address

of teletext packets and further decodes the 8 × 4 hamming

coded words of the packet. This feature can be disabled using

the WST_PKT_DECODE_DISABLE bit (Bit 3, Register 0x60,

user sub map). This feature is valid for WST only.

WST_PKT_DECODE_DISABLE, Disable Hamming

Decoding of Bytes in WST—Address 0x60, Bit 3,

Interrupt/VDP Map

Setting WST_PKT_DECODE_DISABLE to 0 enables hamming

decoding of WST packets.

Setting WST_PKT_DECODE_DISABLE to 1 (default) disables

hamming decoding of WST packets.

For hamming coded bytes, the dehammed nibbles are output

along with some error information from the hamming decoder

as follows:



Input hamming coded byte: {D3, P3, D2, P2, D1, P1, D0, P0}

(bits in decoded order)



Output dehammed byte: {E1, E0, 0, 0, D3', D2', D1', D0'}

(Di' – corrected bits, Ei error information).

Table 86. Error Bits in the Dehammed Output Byte

E[1:0]

Error Information

No errors detected

Error in P4

Double error1

Single error found and corrected

1 The hamming decoder cannot correct for two decoding errors.

ADV7182ABCPZ Datasheet(PDF) 58 Page - Analog Devices

ADV7182ABCPZ Datasheet(HTML) 58 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL