ADV7182ABCPZ datasheet(16/102 Pages) AD

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ADV7182A

Data Sheet

Rev. 0 | Page 16 of 102

ANALOG FRONT END

INPUT CONFIGURATION

The following two steps are crucial for configuring the

ADV7182A to correctly decode the input video.

Use INSEL[4:0] to configure the routing and format decoding

(CVBS, S-Video, or YPrPb).

If the input requirements are not met using the INSEL[4:0]

options, the analog input muxing section must be configured

manually to correctly route the video from the analog input

pins to the ADC. Using the INSEL[4:0] selection, configure

the SDP block, which decodes the digital data, to process

the CVBS, S-Video or YPrPb format.

INSEL[4:0], Input Control—Address 0x00, Bits[4:0]

The INSEL bits allow the user to select the input format. They also

configure the SDP core to process CVBS, differential CVBS,

S-Video (Y/C), or component (YPrPb) format.

INSEL[4:0] has predefined analog input routing schemes that

do not require manual mux programming (see Table 10). This

allows the user to route the various video signal types to the

decoder and select them using INSEL[4:0] only. The added

benefit is that if, for example, the CVBS input is selected, the

remaining channels are powered down.

Table 10. INSEL[4:0]

INSEL[4:0]

Video Format

Analog Input

00000

CVBS

CVBS input on AIN1

00001

CVBS

CVBS input on AIN2

00010

CVBS

CVBS input on AIN3

00011

CVBS

CVBS input on AIN4

01000

S-Video (Y/C)

Y input on AIN1

C input on AIN2

01001

S-Video (Y/C)

Y input on AIN3

C input on AIN4

01100

YPrPb

Y input on AIN1

Pb input on AIN2

Pr input on AIN3

01110

Differential CVBS

Positive on AIN1

Negative on AIN2

01111

Differential CVBS

Positive on AIN3

Negative on AIN4

ANALOG INPUT MUXING

The ADV7182A has an integrated analog muxing section that

allows more than one source of video signal to be connected to

the decoder.

A maximum of four CVBS inputs can be connected to and

decoded by the ADV7182A. As shown in the Pin Configuration

and Function Description section, these analog input pins lie in

close proximity to one another, which requires careful design of the

PCB layout. For example, route ground shielding between all

signals through tracks that are physically close together. It is

strongly recommended that any unused analog input pins be

connected to AGND to act as a shield.

Figure 8. Manual Muxing

MAN_MUX_EN, Manual Input Muxing Enable—

Address 0xC4, Bit 7

To configure the ADV7182A analog muxing section, the user

must select the analog input AIN1 to AIN8 that is to be processed

by the ADC. MAN_MUX_EN must be set to 1 to enable the

following muxing blocks:



MUX_0[2:0], ADC mux configuration (Address 0xC3,

Bits[2:0])



MUX_1[2:0], ADC mux configuration (Address 0xC3,

Bits[6:4])



MUX_2[2:0], ADC mux configuration (Address 0xC4,

Bits[2:0])



MUX_3[2:0], ADC mux configuration (Address 0x60,

Bits[2:0])

The four mux sections are controlled by the signal buses,

MUX_0/MUX_1/MUX_2/MUX_3[2:0]. Table 11 explains the

control words used.

The input signal that contains the timing information (HS and VS)

must be processed by MUX_0. For example, in an S-Video

input configuration, connect MUX_0 to the Y channel and

MUX_1 to the C channel. When one or more muxes are not used

to process video, such as the CVBS input, the idle mux and

associated channel clamps and buffers must be powered down

(see the description of Register 0x3A in Table 96).

AIN1

AIN2

AIN3

AIN4

AIN2

MAN_MUX_EN

MUX_0[2:0]

MUX_3[2:0]

AIN2

AIN4

MUX_1[2:0]

AIN2

AIN3

MUX_2[2:0]

ADC

ADV7182ABCPZ Datasheet(PDF) 16 Page - Analog Devices

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