R5F72115D160FPV datasheet(478/1228 Pages) RENESAS

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Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 2.00 May. 08, 2008 Page 454 of 1200

REJ09B0344-0200

TCLKC

TCNT_2

FFFD

TCNT_1

0001

TCLKD

FFFE

FFFF

0000

0001

0002

0001

0000

FFFF

0000

Figure 10.21 Cascaded Operation Example (a)

(3)

Cascaded Operation Example (b)

Figure 10.22 illustrates the operation when TCNT_1 and TCNT_2 have been cascaded and the

I2AE bit in TICCR has been set to 1 to include the TIOC2A pin in the TGRA_1 input capture

conditions. In this example, the IOA0 to IOA3 bits in TIOR_1 have selected the TIOC1A rising

edge for the input capture timing while the IOA0 to IOA3 bits in TIOR_2 have selected the

TIOC2A rising edge for the input capture timing.

Under these conditions, the rising edge of both TIOC1A and TIOC2A is used for the TGRA_1

input capture condition. For the TGRA_2 input capture condition, the TIOC2A rising edge is used.

TCNT_2 value

H'0000

TGRA_1

TGRA_2

Time

TIOC1A

TIOC2A

TCNT_1

H'0514

H'0513

H'0512

H'0513

H'0512

H'C256

H'FFFF

H'6128

As I1AE in TICCR is 0, data is not captured in TGRA_2 at the TIOC1A input timing.

Figure 10.22 Cascaded Operation Example (b)

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