R5F72115D160FPV datasheet(477/1228 Pages) RENESAS

477 / 1228 page

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 2.00 May. 08, 2008 Page 453 of 1200

REJ09B0344-0200

Table 10.45 show the TICCR setting and input capture input pins.

Table 10.45 TICCR Setting and Input Capture Input Pins

Target Input Capture

TICCR Setting

Input Capture Input Pins

I2AE bit = 0 (initial value)

TIOC1A

Input capture from TCNT_1 to

TGRA_1

I2AE bit = 1

TIOC1A, TIOC2A

I2BE bit = 0 (initial value)

TIOC1B

Input capture from TCNT_1 to

TGRB_1

I2BE bit = 1

TIOC1B, TIOC2B

I1AE bit = 0 (initial value)

TIOC2A

Input capture from TCNT_2 to

TGRA_2

I1AE bit = 1

TIOC2A, TIOC1A

I1BE bit = 0 (initial value)

TIOC2B

Input capture from TCNT_2 to

TGRB_2

I1BE bit = 1

TIOC2B, TIOC1B

(1)

Example of Cascaded Operation Setting Procedure

Figure 10.20 shows an example of the setting procedure for cascaded operation.

Cascaded operation

Set cascading

Start count

[1]

[2]

[1] Set bits TPSC2 to TPSC0 in the channel 1

TCR to B'1111 to select TCNT_2 overflow/

underflow counting.

[2] Set the CST bit in TSTR for the upper and

lower channel to 1 to start the count

operation.

Figure 10.20 Cascaded Operation Setting Procedure

(2)

Cascaded Operation Example (a)

Figure 10.21 illustrates the operation when TCNT_2 overflow/underflow counting has been set for

TCNT_1 and phase counting mode has been designated for channel 2.

TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow.

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