R5F72115D160FPV datasheet(476/1228 Pages) RENESAS

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Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 2.00 May. 08, 2008 Page 452 of 1200

REJ09B0344-0200

TCNT_0 value

H'0000

TGRA_0

Time

TIOCA

TGRC_0

H'0520

H'0450

H'0200

H'0520

H'0450

H'0200

TGRB_0

TGRA_0

Transfer

Figure 10.19 Example of Buffer Operation When TCNT_0 Clearing is Selected for

TGRC_0 to TGRA_0 Transfer Timing

10.4.4

Cascaded Operation

In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit

counter.

This function works by counting the channel 1 counter clock upon overflow/underflow of

TCNT_2 as set in bits TPSC0 to TPSC2 in TCR.

Underflow occurs only when the lower 16-bit TCNT is in phase counting mode.

Table 10.44 shows the register combinations used in cascaded operation.

Note:

When phase counting mode is set for channel 1, the counter clock setting is invalid and the

counters operates independently in phase counting mode.

Table 10.44 Cascaded Combinations

Combination

Upper 16 Bits

Lower 16 Bits

Channels 1 and 2

TCNT_1

TCNT_2

For simultaneous input capture of TCNT_1 and TCNT_2 during cascaded operation, additional

input capture input pins can be specified by the input capture control register (TICCR). For input

capture in cascade connection, refer to section 10.7.22, Simultaneous Capture of TCNT_1 and

TCNT_2 in Cascade Connection.

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