R5F72115D160FPV datasheet(475/1228 Pages) RENESAS

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Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 2.00 May. 08, 2008 Page 451 of 1200

REJ09B0344-0200

TCNT value

H'09FB

H'0000

TGRC

Time

H'0532

TIOCA

TGRA

H'0F07

H'0532

H'0F07

H'0532

H'0F07

H'09FB

Figure 10.18 Example of Buffer Operation (2)

(3)

Selecting Timing for Transfer from Buffer Registers to Timer General Registers in

Buffer Operation

The timing for transfer from buffer registers to timer general registers can be selected in PWM

mode 1 or 2 for channel 0 or in PWM mode 1 for channels 3 and 4 by setting the buffer operation

transfer mode registers (TBTM_0, TBTM_3, and TBTM_4). Either compare match (initial

setting) or TCNT clearing can be selected for the transfer timing. TCNT clearing as transfer

timing is one of the following cases.

• When TCNT overflows (H'FFFF to H'0000)

• When H'0000 is written to TCNT during counting

• When TCNT is cleared to H'0000 under the condition specified in the CCLR2 to CCLR0 bits

in TCR

Note:

TBTM must be modified only while TCNT stops.

Figure 10.19 shows an operation example in which PWM mode 1 is designated for channel 0 and

buffer operation is designated for TGRA_0 and TGRC_0. The settings used in this example are

TCNT_0 clearing by compare match B, 1 output at compare match A, and 0 output at compare

match B. The TTSA bit in TBTM_0 is set to 1.

R5F72115D160FPV Datasheet(PDF) 475 Page - Renesas Technology Corp